| /src/sys/arch/arm/arm/ |
| process_machdep.c | 161 regs->r_cpsr = tf->tf_spsr;
163 KASSERT(VALID_PSR(tf->tf_spsr));
166 if (tf->tf_spsr & PSR_T_bit)
199 tf->tf_spsr &= ~(PSR_FLAGS | PSR_T_bit);
200 tf->tf_spsr |= regs->r_cpsr & PSR_FLAGS;
203 tf->tf_spsr |= PSR_T_bit;
205 KASSERT(VALID_PSR(tf->tf_spsr));
234 tf->tf_spsr |= PSR_T_bit;
236 tf->tf_spsr &= ~PSR_T_bit;
|
| ast.c | 94 KASSERT(VALID_PSR(lwp_trapframe(l)->tf_spsr));
111 KASSERT(VALID_PSR(tf->tf_spsr));
|
| syscall.c | 104 KASSERT(VALID_PSR(tf->tf_spsr));
105 restore_interrupts(tf->tf_spsr & IF32_bits);
131 if (tf->tf_spsr & PSR_T_bit) {
212 if (tf->tf_spsr & PSR_T_bit)
256 tf->tf_spsr &= ~PSR_C_bit; /* carry bit */
264 if (tf->tf_spsr & PSR_T_bit)
278 tf->tf_spsr |= PSR_C_bit; /* carry bit */
291 tf->tf_spsr &= ~PSR_C_bit; /* carry bit */
|
| undefined.c | 131 if (tf->tf_spsr & PSR_T_bit)
182 if (tf->tf_spsr & PSR_T_bit) {
270 if (!arm_cond_ok_p(__SHIFTIN(insn, INSN_COND_MASK), frame->tf_spsr)) {
316 if ((tf->tf_spsr & PSR_MODE) != PSR_USR32_MODE) {
325 restore_interrupts(tf->tf_spsr & IF32_bits);
328 if (tf->tf_spsr & PSR_T_bit)
341 if ((tf->tf_spsr & PSR_MODE) == PSR_USR32_MODE) {
348 if (tf->tf_spsr & PSR_T_bit) {
387 if ((tf->tf_spsr & PSR_T_bit) && !CPU_IS_ARMV7_P()) {
409 } else if ((tf->tf_spsr & PSR_T_bit) && !CPU_IS_ARMV7_P())
[all...] |
| arm_machdep.c | 179 tf->tf_spsr = PSR_USR32_MODE;
185 tf->tf_spsr |= PSR_E_BIT;
190 tf->tf_spsr |= PSR_T_bit;
|
| compat_16_machdep.c | 121 frame.sf_sc.sc_spsr = tf->tf_spsr;
170 tf->tf_spsr |= PSR_T_bit;
172 tf->tf_spsr &= ~PSR_T_bit;
257 tf->tf_spsr = context.sc_spsr;
|
| sig_machdep.c | 147 tf->tf_spsr |= PSR_T_bit;
149 tf->tf_spsr &= ~PSR_T_bit;
183 gr[_REG_CPSR] = tf->tf_spsr;
251 tf->tf_spsr = gr[_REG_CPSR];
|
| compat_13_machdep.c | 100 tf->tf_spsr = context.sc_spsr;
|
| /src/sys/arch/arm/include/ |
| frame.h | 54 register_t tf_spsr; member in struct:trapframe
82 #define TRAP_USERMODE(tf) (((tf)->tf_spsr & PSR_MODE) == PSR_USR32_MODE)
|
| cpu.h | 119 #define CLKF_USERMODE(cf) (((cf)->cf_tf.tf_spsr & PSR_MODE) == PSR_USR32_MODE)
129 ((cf)->cf_tf.tf_spsr & PSR_MODE) == PSR_UND32_MODE)
|
| /src/sys/arch/arm/arm32/ |
| fault.c | 183 tf->tf_spsr);
206 if (tf->tf_spsr & PSR_T_bit) {
253 KASSERT(!TRAP_USERMODE(tf) || VALID_PSR(tf->tf_spsr));
255 if (__predict_true((tf->tf_spsr & I32_bit) != I32_bit))
256 restore_interrupts(tf->tf_spsr & IF32_bits);
258 if (__predict_true((tf->tf_spsr & IF32_bits) != IF32_bits))
259 restore_interrupts(tf->tf_spsr & IF32_bits);
377 if (__predict_false((tf->tf_spsr & PSR_MODE)==PSR_UND32_MODE)) {
415 if (__predict_false(tf->tf_spsr & PSR_T_bit)) {
582 printf("spsr=%08x\n", tf->tf_spsr);
[all...] |
| kgdb_machdep.c | 113 gdb_regs[KGDB_REGNUM_SPSR] = regs->tf_spsr;
139 regs->tf_spsr = gdb_regs[KGDB_REGNUM_SPSR];
|
| arm32_boot.c | 194 tf->tf_spsr = PSR_USR32_MODE;
196 tf->tf_spsr |= PSR_E_BIT;
|
| db_machdep.c | 86 { "spsr", XO(tf_spsr), ddb_reg_var, NULL },
161 db_printf("spsr=%08x\n", frame->tf_spsr);
477 if (DDB_REGS->tf_spsr & PSR_T_bit) {
|
| /src/sys/arch/aarch64/include/ |
| frame.h | 47 #define tf_spsr tf_regs.r_spsr macro
|
| cpu.h | 58 #define CLKF_USERMODE(cf) ((((cf)->cf_tf.tf_spsr) & 0x0f) == 0)
|
| /src/sys/arch/aarch64/aarch64/ |
| process_machdep.c | 95 lwp_trapframe(l)->tf_spsr |= SPSR_SS;
97 lwp_trapframe(l)->tf_spsr &= ~SPSR_SS;
|
| syscall.c | 77 tf->tf_spsr &= ~NZCV_C;
157 tf->tf_spsr &= ~NZCV_C;
178 tf->tf_spsr |= NZCV_C;
|
| netbsd32_machdep.c | 89 tf->tf_spsr = SPSR_M_USR32 | SPSR_A32_E;
91 tf->tf_spsr = SPSR_M_USR32;
96 tf->tf_spsr |= SPSR_A32_T;
146 regs->r_cpsr = tf->tf_spsr;
149 if (tf->tf_spsr & SPSR_A32_T)
219 tf->tf_spsr &= ~(SPSR_NZCV | SPSR_A32_T);
220 tf->tf_spsr |= regs->r_cpsr & (SPSR_NZCV | SPSR_A32_T);
224 tf->tf_spsr |= SPSR_A32_T;
365 tf->tf_spsr |= SPSR_A32_T;
367 tf->tf_spsr &= ~SPSR_A32_T
[all...] |
| aarch32_syscall.c | 72 thumbmode = (tf->tf_spsr & SPSR_A32_T) ? true : false;
200 tf->tf_spsr &= ~NZCV_C;
222 tf->tf_spsr |= NZCV_C;
|
| fault.c | 140 const bool user = IS_SPSR_USER(tf->tf_spsr) ? true : false;
193 (tf->tf_spsr & SPSR_PAN))) {
365 ": %s", strdisasm(tf->tf_pc, tf->tf_spsr));
|
| trap.c | 204 if (!(tf->tf_spsr & SPSR_I))
463 tf->tf_spsr &= ~SPSR_SS;
493 strdisasm(tf->tf_pc, tf->tf_spsr));
747 insn_size = fetch_arm_insn(tf->tf_pc, tf->tf_spsr, &insn);
750 if (tf->tf_spsr & SPSR_A32_T)
768 if (arm_cond_match(insn, tf->tf_spsr)) {
781 if (arm_cond_match(insn, tf->tf_spsr)) {
790 if (arm_cond_match(insn, tf->tf_spsr)) {
799 if (arm_cond_match(insn, tf->tf_spsr)) {
907 strdisasm(tf->tf_pc, tf->tf_spsr));
[all...] |
| exec_machdep.c | 159 tf->tf_spsr = SPSR_M_EL0T;
|
| /src/sys/arch/arm/xscale/ |
| i80321_icu.c | 403 frame->cf_tf.tf_spsr |= I32_bit;
438 frame->cf_tf.tf_spsr &= ~I32_bit;
|
| /src/sys/compat/linux/arch/arm/ |
| linux_machdep.c | 129 frame.sf_sc.sc_cpsr = tf->tf_spsr;
239 tf->tf_spsr = frame.sf_sc.sc_cpsr;
|
