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    Searched refs:tiled (Results 1 - 8 of 8) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/i915/gvt/
fb_decoder.c 152 u32 tiled, int stride_mask, int bpp)
160 switch (tiled) {
180 tiled);
224 plane->tiled = val & PLANE_CTL_TILED_MASK;
239 plane->tiled = val & DISPPLANE_TILED;
263 plane->stride = intel_vgpu_get_stride(vgpu, pipe, plane->tiled,
433 plane->tiled = !!(val & SPRITE_TILED);
fb_decoder.h 108 u32 tiled; /* tiling mode: linear, X-tiled, Y tiled, etc */ member in struct:intel_vgpu_primary_plane_format
123 u8 tiled; /* X-tiled */ member in struct:intel_vgpu_sprite_plane_format
dmabuf.c 290 switch (p.tiled) {
307 gvt_vgpu_err("invalid tiling mode: %x\n", p.tiled);
  /src/sys/external/bsd/drm2/dist/drm/radeon/
radeon_fb.c 100 int radeon_align_pitch(struct radeon_device *rdev, int width, int cpp, bool tiled)
103 int align_large = (ASIC_IS_AVIVO(rdev)) || tiled;
radeon_r600_cs.c 2383 u32 header, cmd, count, tiled; local in function:r600_dma_cs_parse
2399 tiled = GET_DMA_T(header);
2408 if (tiled) {
2439 if (tiled) {
2443 /* tiled src, linear dst */
2453 /* linear src, tiled dst */
radeon_mode.h 990 int radeon_align_pitch(struct radeon_device *rdev, int width, int bpp, bool tiled);
  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_fb.c 98 int amdgpu_align_pitch(struct amdgpu_device *adev, int width, int cpp, bool tiled)
amdgpu_mode.h 624 int amdgpu_align_pitch(struct amdgpu_device *adev, int width, int bpp, bool tiled);

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