| /src/sys/external/bsd/drm2/dist/drm/i915/gem/ |
| i915_gem_tiling.c | 24 * DOC: buffer object tiling
30 * object, and hence it also doesn't care about tiling or swizzling. There's two
33 * - For X and Y tiling the hardware provides detilers for CPU access, so called
35 * these, and therefore userspace must tell the kernel the object tiling if it
40 * and hence now the tiling. Note that on a subset of platforms with
44 * Since neither of this applies for new tiling layouts on modern platforms like
45 * W, Ys and Yf tiling GEM only allows object tiling to be set to X or Y tiled.
54 * @tiling: tiling mod
[all...] |
| i915_gem_object.h | 235 i915_gem_tile_height(unsigned int tiling)
237 GEM_BUG_ON(!tiling);
238 return tiling == I915_TILING_Y ? 32 : 8;
255 unsigned int tiling, unsigned int stride);
|
| /src/sys/external/bsd/drm2/dist/drm/i915/gem/selftests/ |
| i915_gem_mman.c | 29 unsigned int tiling; member in struct:tile
42 if (tile->tiling == I915_TILING_NONE)
48 if (tile->tiling == I915_TILING_X) {
101 err = i915_gem_object_set_tiling(obj, tile->tiling, tile->stride);
103 pr_err("Failed to set tiling mode=%u, stride=%u, err=%d\n",
104 tile->tiling, tile->stride, err);
108 GEM_BUG_ON(i915_gem_object_get_tiling(obj) != tile->tiling);
154 pr_err("Partial view for %lu [%u] (offset=%llu, size=%u [%llu, row size %u], fence=%d, tiling=%d, stride=%d) misalignment, expected write to page (%llu + %u [0x%llx]) of 0x%x, found 0x%x\n",
159 tile->tiling ? tile_row_pages(obj) : 0,
160 vma->fence ? vma->fence->id : -1, tile->tiling, tile->stride
309 int tiling; local in function:igt_partial_tiling
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/i915/ |
| i915_gem_fence_reg.c | 50 * have their own tiling state bits and don't need fences.
52 * Also note that fences only support X and Y tiling and hence can't be used for
53 * the fancier new tiling formats like W, Ys and Yf.
142 unsigned int tiling = i915_gem_object_get_tiling(vma->obj); local in function:i915_write_fence_reg
143 bool is_y_tiled = tiling == I915_TILING_Y;
248 "bogus fence setup with stride: 0x%x, tiling mode: %i\n",
409 * and tiling format.
515 * Commit delayed tiling changes if we have an object still
527 * DOC: tiling swizzling details
529 * The idea behind tiling is to increase cache hit rates by rearrangin
[all...] |
| i915_drv.h | 1720 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
1993 unsigned int tiling, unsigned int stride);
1995 unsigned int tiling, unsigned int stride);
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dml/dcn20/ |
| amdgpu_display_rq_dlg_calc_20.c | 330 unsigned int tiling,
335 bool surf_linear = (tiling == dm_sw_linear);
406 (enum dm_swizzle_mode)(tiling),
444 if (tiling != dm_sw_linear)
|
| amdgpu_display_rq_dlg_calc_20v2.c | 330 unsigned int tiling,
335 bool surf_linear = (tiling == dm_sw_linear);
406 (enum dm_swizzle_mode)(tiling),
444 if (tiling != dm_sw_linear)
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dml/dcn21/ |
| amdgpu_display_rq_dlg_calc_21.c | 317 unsigned int tiling,
323 bool surf_linear = (tiling == dm_sw_linear);
398 (enum dm_swizzle_mode) (tiling),
436 if (tiling != dm_sw_linear)
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dml/ |
| amdgpu_dml1_display_rq_dlg_calc.c | 376 int tiling,
381 bool surf_linear = (tiling == dm_sw_linear);
432 if (tiling != dm_sw_linear)
|
| /src/sys/external/bsd/drm2/dist/drm/i915/display/ |
| intel_display.c | 3432 switch (plane_config->tiling) {
3437 obj->tiling_and_stride = fb->pitches[0] | plane_config->tiling;
3440 MISSING_CASE(plane_config->tiling);
3641 if (plane_config->tiling)
3841 DRM_DEBUG_KMS("Unable to find suitable display surface offset due to X-tiling\n");
9117 plane_config->tiling = I915_TILING_X;
9137 if (plane_config->tiling)
10289 u32 val, base, offset __unused, stride_mult, tiling, alpha; local in function:skl_get_initial_plane_config
10328 tiling = val & PLANE_CTL_TILED_MASK;
10329 switch (tiling) {
16937 unsigned int tiling, stride; local in function:intel_framebuffer_init
[all...] |
| intel_display_types.h | 617 unsigned int tiling; member in struct:intel_initial_plane_config
|
