| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/core/ |
| amdgpu_dc_debug.c | 135 "plane_state->tiling_info.gfx8.num_banks = %d;\n"
136 "plane_state->tiling_info.gfx8.bank_width = %d;\n"
137 "plane_state->tiling_info.gfx8.bank_width_c = %d;\n"
138 "plane_state->tiling_info.gfx8.bank_height = %d;\n"
139 "plane_state->tiling_info.gfx8.bank_height_c = %d;\n"
140 "plane_state->tiling_info.gfx8.tile_aspect = %d;\n"
141 "plane_state->tiling_info.gfx8.tile_aspect_c = %d;\n"
142 "plane_state->tiling_info.gfx8.tile_split = %d;\n"
143 "plane_state->tiling_info.gfx8.tile_split_c = %d;\n"
144 "plane_state->tiling_info.gfx8.tile_mode = %d;\n
[all...] |
| amdgpu_dc.c | 1562 if (memcmp(&u->plane_info->tiling_info, &u->surface->tiling_info,
1570 if (u->plane_info->tiling_info.gfx9.swizzle != DC_SW_LINEAR) {
1863 surface->tiling_info =
1864 srf_update->plane_info->tiling_info;
|
| amdgpu_dc_resource.c | 2118 pipe_ctx->plane_state->tiling_info.gfx9.swizzle == DC_SW_UNKNOWN) {
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/inc/hw/ |
| hubp.h | 120 union dc_tiling_info *tiling_info,
134 union dc_tiling_info *tiling_info,
|
| mem_input.h | 142 union dc_tiling_info *tiling_info,
156 union dc_tiling_info *tiling_info,
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce/ |
| amdgpu_dce_mem_input.c | 106 union dc_tiling_info *tiling_info)
108 switch (tiling_info->gfx8.array_mode) {
141 union dc_tiling_info *tiling_info,
146 enum mi_tiling_format mi_tiling = get_mi_tiling(tiling_info);
512 union dc_tiling_info *tiling_info,
521 program_tiling(dce_mi, tiling_info);
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce110/ |
| amdgpu_dce110_mem_input_v.c | 532 union dc_tiling_info *tiling_info,
550 switch (tiling_info->gfx8.array_mode) {
572 union dc_tiling_info *tiling_info,
576 const unsigned int *pte = get_dvmm_hw_setting(tiling_info, format, false);
577 const unsigned int *pte_chroma = get_dvmm_hw_setting(tiling_info, format, true);
645 union dc_tiling_info *tiling_info,
654 program_tiling(mem_input110, tiling_info, format);
|
| amdgpu_dce110_hw_sequencer.c | 1837 if (pipe_ctx->plane_state->tiling_info.gfx8.array_mode == DC_ARRAY_LINEAR_GENERAL)
2506 &plane_state->tiling_info,
2518 &plane_state->tiling_info,
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/amdgpu_dm/ |
| amdgpu_dm.c | 3146 const union dc_tiling_info *tiling_info,
3173 input.swizzle_mode = tiling_info->gfx9.swizzle;
3207 union dc_tiling_info *tiling_info,
3215 memset(tiling_info, 0, sizeof(*tiling_info));
3272 tiling_info->gfx8.num_banks = num_banks;
3273 tiling_info->gfx8.array_mode =
3275 tiling_info->gfx8.tile_split = tile_split;
3276 tiling_info->gfx8.bank_width = bankw;
3277 tiling_info->gfx8.bank_height = bankh
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/ |
| dc.h | 748 union dc_tiling_info tiling_info; member in struct:dc_plane_state
796 union dc_tiling_info tiling_info; member in struct:dc_plane_info
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn20/ |
| dcn20_hubp.h | 296 union dc_tiling_info *tiling_info,
|
| amdgpu_dcn20_hubp.c | 524 union dc_tiling_info *tiling_info,
534 hubp2_program_tiling(hubp2, tiling_info, format);
|
| amdgpu_dcn20_resource.c | 2163 swizzle_mode_to_macro_tile_size(pln->tiling_info.gfx9.swizzle);
2164 swizzle_to_dml_params(pln->tiling_info.gfx9.swizzle,
3049 plane_state->tiling_info.gfx9.swizzle = swizzle;
|
| amdgpu_dcn20_hwseq.c | 1450 &plane_state->tiling_info,
|
| /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/ |
| amdgpu_gem.c | 489 amdgpu_bo_get_tiling_flags(robj, &args->data.tiling_info);
499 r = amdgpu_bo_set_tiling_flags(robj, args->data.tiling_info);
|
| /src/sys/external/bsd/drm2/dist/include/uapi/drm/ |
| amdgpu_drm.h | 370 __u64 tiling_info; member in struct:drm_amdgpu_gem_metadata::__anonf5ca36750308
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn10/ |
| amdgpu_dcn10_hubp.c | 531 union dc_tiling_info *tiling_info,
539 hubp1_program_tiling(hubp, tiling_info, format);
|
| dcn10_hubp.h | 694 union dc_tiling_info *tiling_info,
|
| amdgpu_dcn10_resource.c | 1255 plane_state->tiling_info.gfx9.swizzle = swizzle;
|
| amdgpu_dcn10_hw_sequencer.c | 2347 &plane_state->tiling_info,
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/calcs/ |
| amdgpu_dcn_calcs.c | 336 input->src.sw_mode = pipe->plane_state->tiling_info.gfx9.swizzle;
345 input->src.macro_tile_size = swizzle_mode_to_macro_tile_size(pipe->plane_state->tiling_info.gfx9.swizzle);
984 pipe->plane_state->tiling_info.gfx9.swizzle);
|
