| /src/sys/arch/powerpc/include/ibm4xx/ |
| Makefile | 5 INCS= cpu.h pmap.h spr.h tlb.h
|
| pmap.h | 80 #include <powerpc/ibm4xx/tlb.h>
82 #define KERNEL_PID 1 /* TLB PID to use for kernel translation */
85 * A TTE is a 16KB or greater TLB entry w/size and endianness bits
146 volatile int pm_ctx; /* PID to identify PMAP's entries in TLB */
189 * Alternate mapping hooks for pool pages. Avoids thrashing the TLB.
|
| /src/sys/arch/mips/mips/ |
| wired_map.c | 93 struct tlbmask tlb; local in function:mips3_wired_enter_page
101 /* TLB entries come in pairs: this is the first address of the pair */
148 tlb.tlb_mask = mips3_wired_map[index].pgmask;
149 tlb.tlb_hi = mips3_vad_to_vpn(va0);
151 tlb.tlb_lo0 = MIPS3_PG_G;
153 tlb.tlb_lo0 =
158 tlb.tlb_lo1 = MIPS3_PG_G;
160 tlb.tlb_lo1 = mips3_paddr_to_tlbpfn(
164 tlb_write_entry(MIPS3_TLB_WIRED_UPAGES + index, &tlb);
|
| db_interface.c | 261 struct tlbmask tlb; local in function:db_tlbdump_cmd
272 tlb_read_entry(i, &tlb);
273 if (valid_only && !(tlb.tlb_lo1 & MIPS1_PG_V))
275 db_printf("TLB%c%2d Hi 0x%08x Lo 0x%08x",
276 (tlb.tlb_lo1 & MIPS1_PG_V) ? ' ' : '*',
277 i, tlb.tlb_hi,
278 tlb.tlb_lo1 & MIPS1_PG_FRAME);
280 (tlb.tlb_lo1 & MIPS1_PG_D) ? 'D' : ' ',
281 (tlb.tlb_lo1 & MIPS1_PG_G) ? 'G' : ' ',
282 (tlb.tlb_lo1 & MIPS1_PG_N) ? 'N' : ' ')
[all...] |
| /src/sys/arch/emips/emips/ |
| xs_bee3.c | 111 * Map the USART 1:1, we just turned on the TLB.
112 * NB: This must be a wired TLB entry lest we lose it before autoconf().
118 struct tlbmask tlb; local in function:xs_bee3_cons_init
120 tlb.tlb_hi = USART_DEFAULT_ADDRESS;
121 tlb.tlb_lo0 = USART_DEFAULT_ADDRESS | 0xf02;
122 tlb_write_entry(3, &tlb);
|
| interrupt.c | 80 struct tlbmask tlb; local in function:intr_init
85 tlb.tlb_hi = INTERRUPT_CONTROLLER_DEFAULT_ADDRESS;
86 tlb.tlb_lo0 = INTERRUPT_CONTROLLER_DEFAULT_ADDRESS | 0xf02;
87 tlb_write_entry(4, &tlb);
89 tlb.tlb_hi = TIMER_DEFAULT_ADDRESS;
90 tlb.tlb_lo0 = TIMER_DEFAULT_ADDRESS | 0xf02;
91 tlb_write_entry(5, &tlb);
|
| xilinx_ml40x.c | 114 * Map the USART 1:1, we just turned on the TLB.
115 * NB: This must be a wired TLB entry lest we lose it before autoconf().
121 struct tlbmask tlb; local in function:xilinx_ml40x_cons_init
123 tlb.tlb_hi = USART_DEFAULT_ADDRESS;
124 tlb.tlb_lo0 = USART_DEFAULT_ADDRESS | 0xf02;
125 tlb_write_entry(3, &tlb);
|
| /src/sys/arch/arm/arm/ |
| cpufunc_asm_fa526.S | 38 cmp r1, #0 @ need to flush the cache / tlb?
48 /* If we have updated the TTB we must flush the TLB */
49 mcrne p15, 0, r1, c8, c7, 0 /* invalidate I+D TLB */
58 * TLB functions
70 * TLB functions
223 /* If we have updated the TTB we must flush the TLB */
225 mcr p15, 0, r0, c8, c7, 0 /* flush the I+D tlb */
|
| cpufunc_asm_armv7.S | 68 mcr p15, 0, r0, c8, c7, 2 @ flush I+D tlb all ASID
76 mcr p15, 0, r0, c8, c3, 2 @ flush I+D tlb all ASID
88 mcr p15, 0, r0, c8, c7, 1 @ flush I+D tlb single entry
91 mcr p15, 0, r0, c8, c7, 1 @ flush I+D tlb single entry
103 mcr p15, 0, r0, c8, c3, 1 @ flush I+D tlb single entry
106 mcr p15, 0, r0, c8, c3, 1 @ flush I+D tlb single entry
119 mcr p15, 0, r0, c8, c6, 0 @ flush entire D tlb
129 mcr p15, 0, r0, c8, c7, 0 @ flush entire I+D tlb
141 mcr p15, 0, r0, c8, c3, 0 @ flush entire I+D tlb, IS
|
| /src/sys/arch/hppa/include/ |
| pte.h | 35 #define PTE_PROT(tlb) ((tlb) >> PTE_PROT_SHIFT)
42 /* TLB access/protection values */
|
| /src/sys/external/gpl2/dts/dist/arch/riscv/boot/dts/sifive/ |
| fu540-c000.dtsi | 48 d-tlb-sets = <1>;
49 d-tlb-size = <32>;
54 i-tlb-sets = <1>;
55 i-tlb-size = <32>;
62 tlb-split;
75 d-tlb-sets = <1>;
76 d-tlb-size = <32>;
81 i-tlb-sets = <1>;
82 i-tlb-size = <32>;
89 tlb-split
[all...] |
| fu740-c000.dtsi | 49 d-tlb-sets = <1>;
50 d-tlb-size = <40>;
55 i-tlb-sets = <1>;
56 i-tlb-size = <40>;
64 tlb-split;
76 d-tlb-sets = <1>;
77 d-tlb-size = <40>;
82 i-tlb-sets = <1>;
83 i-tlb-size = <40>;
91 tlb-split
[all...] |
| /src/sys/arch/ews4800mips/stand/common/ |
| cop0.c | 39 struct tlb { struct
48 static void __tlb_pagemask(struct tlb *);
52 EWS4800/350. IPL don't handle TLB refill exception.
72 struct tlb *e;
81 case 'r': /* Read TLB entry all. */
86 case 'd': /* Dump TLB summary */
97 case 'p': /* Print TLB entry */
99 printf("tlb p entry#.\n");
143 __tlb_pagemask(struct tlb *e)
|
| /src/sys/arch/powerpc/booke/ |
| booke_stubs.c | 107 tlb_read_entry(size_t pos, struct tlbmask *tlb)
109 (*cpu_md_ops.md_tlb_ops->md_tlb_read_entry)(pos, tlb);
115 tlb_write_entry(size_t pos, const struct tlbmask *tlb)
117 (*cpu_md_ops.md_tlb_ops->md_tlb_write_entry)(pos, tlb);
|
| e500_tlb.c | 110 struct e500_tlb tlb; local in function:hwtlb_to_tlb
114 tlb.tlb_va = MAS2_EPN & hwtlb.hwtlb_mas2;
115 tlb.tlb_size = 1024 << (2 * MASX_TSIZE_GET(hwtlb.hwtlb_mas1));
116 tlb.tlb_asid = MASX_TID_GET(hwtlb.hwtlb_mas1);
117 tlb.tlb_pte = (hwtlb.hwtlb_mas2 & MAS2_WIMGE)
126 tlb.tlb_pte |= (prot_mask & hwtlb.hwtlb_mas3) << prot_shift;
127 return tlb;
147 * If tlbassoc is the same as tlbentries (like in TLB1) then the TLB is
149 * is less than the number of tlb entries, the slot is split in two
150 * fields. Since the TLB is M rows by N ways, the lowers bits are fo
619 struct e500_tlb tlb = hwtlb_to_tlb(hwtlb); local in function:e500_tlb_dump
668 struct e500_tlb tlb = hwtlb_to_tlb(hwtlb); local in function:e500_tlb_walk
[all...] |
| /src/sys/external/gpl2/dts/dist/arch/riscv/boot/dts/microchip/ |
| mpfs.dtsi | 44 d-tlb-sets = <1>;
45 d-tlb-size = <32>;
50 i-tlb-sets = <1>;
51 i-tlb-size = <32>;
59 tlb-split;
75 d-tlb-sets = <1>;
76 d-tlb-size = <32>;
81 i-tlb-sets = <1>;
82 i-tlb-size = <32>;
90 tlb-split
[all...] |
| /src/sys/arch/arc/arc/ |
| minidebug.c | 551 printf("tlb-dump\n");
562 printf("tlb");
944 * Dump TLB contents.
950 struct tlb tlb; local in function:arc_dump_tlb
955 mips3_TLBRead(tlbno, &tlb);
956 if (tlb.tlb_lo0 & MIPS3_PG_V || tlb.tlb_lo1 & MIPS3_PG_V) {
957 printf("TLB %2d vad 0x%08x ", tlbno, tlb.tlb_hi)
[all...] |
| /src/sys/arch/sparc64/include/ |
| bootinfo.h | 121 struct tlb_entry tlb[1]; member in struct:btinfo_tlb
|
| /src/sys/external/gpl2/dts/dist/arch/riscv/boot/dts/starfive/ |
| jh7100.dtsi | 26 d-tlb-sets = <1>;
27 d-tlb-size = <32>;
32 i-tlb-sets = <1>;
33 i-tlb-size = <32>;
40 tlb-split;
55 d-tlb-sets = <1>;
56 d-tlb-size = <32>;
61 i-tlb-sets = <1>;
62 i-tlb-size = <32>;
69 tlb-split
[all...] |
| jh7110.dtsi | 49 d-tlb-sets = <1>;
50 d-tlb-size = <40>;
55 i-tlb-sets = <1>;
56 i-tlb-size = <40>;
63 tlb-split;
82 d-tlb-sets = <1>;
83 d-tlb-size = <40>;
88 i-tlb-sets = <1>;
89 i-tlb-size = <40>;
96 tlb-split
[all...] |
| /src/sys/arch/usermode/usermode/ |
| pmap.c | 90 static struct pv_entry **tlb; /* current tlb mappings (direct mapped) */ variable in typeref:struct:pv_entry **
312 thunk_printf_debug("tlb va->pa lookup table is %"PRIu64" KB for "
337 /* set up tlb space */
338 tlb = (struct pv_entry **) kmem_kvm_cur_start;
340 addr = thunk_mmap(tlb, pm_entries_size,
344 if (addr != (void *) tlb)
345 panic("pmap_bootstrap: can't map in tlb entries\n");
347 memset(tlb, 0, pm_entries_size); /* test and clear */
349 thunk_printf_debug("kernel tlb entries initialized correctly\n")
[all...] |
| /src/sys/arch/evbppc/explora/ |
| machdep.c | 52 #include <powerpc/ibm4xx/tlb.h>
|
| /src/sys/arch/evbppc/obs405/ |
| obs266_machdep.c | 92 #include <powerpc/ibm4xx/tlb.h>
|
| /src/sys/arch/evbppc/walnut/ |
| machdep.c | 91 #include <powerpc/ibm4xx/tlb.h>
|
| /src/sys/arch/powerpc/include/booke/ |
| cpuvar.h | 117 #include <uvm/pmap/tlb.h>
|
