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      1 /*-
      2  * Copyright (c) 2013 The NetBSD Foundation, Inc.
      3  * All rights reserved.
      4  *
      5  * This code is derived from software contributed to The NetBSD Foundation
      6  * by Matt Thomas of 3am Software Foundry.
      7  *
      8  * Redistribution and use in source and binary forms, with or without
      9  * modification, are permitted provided that the following conditions
     10  * are met:
     11  * 1. Redistributions of source code must retain the above copyright
     12  *    notice, this list of conditions and the following disclaimer.
     13  * 2. Redistributions in binary form must reproduce the above copyright
     14  *    notice, this list of conditions and the following disclaimer in the
     15  *    documentation and/or other materials provided with the distribution.
     16  *
     17  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
     18  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
     19  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
     20  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
     21  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     22  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     23  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     24  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     25  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     26  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     27  * POSSIBILITY OF SUCH DAMAGE.
     28  */
     29 
     30 #include "opt_cputypes.h"
     31 #include "opt_multiprocessor.h"
     32 
     33 #include <sys/cdefs.h>
     34 __KERNEL_RCSID(1, "$NetBSD: arm32_tlb.c,v 1.16 2026/04/19 15:09:49 skrll Exp $");
     35 
     36 #include <sys/param.h>
     37 #include <sys/types.h>
     38 
     39 #include <uvm/uvm.h>
     40 
     41 #include <arm/locore.h>
     42 
     43 bool arm_has_tlbiasid_p;	// CPU supports TLBIASID system coprocessor op
     44 bool arm_has_mpext_p;		// CPU supports MP extensions
     45 
     46 tlb_asid_t
     47 tlb_get_asid(void)
     48 {
     49 	return (armreg_ttbcr_read() & TTBCR_S_PD0) != 0 ?
     50 	    KERNEL_PID : (armreg_contextidr_read() & 0xff);
     51 }
     52 
     53 #if 0
     54 void
     55 tlb_set_asid(tlb_asid_t asid, pmap_t pm)
     56 {
     57 	dsb(sy);
     58 	if (asid == KERNEL_PID) {
     59 		armreg_ttbcr_write(armreg_ttbcr_read() | TTBCR_S_PD0);
     60 		isb();
     61 	}
     62 	armreg_contextidr_write(asid);
     63 	isb();
     64 }
     65 #endif
     66 
     67 void
     68 tlb_invalidate_all(void)
     69 {
     70 	const bool vivt_icache_p = arm_pcache.icache_type == CACHE_TYPE_VIVT;
     71 	dsb(sy);
     72 	if (arm_has_mpext_p) {
     73 		armreg_tlbiallis_write(0);
     74 	} else {
     75 		armreg_tlbiall_write(0);
     76 	}
     77 	isb();
     78 	if (__predict_false(vivt_icache_p)) {
     79 		if (arm_has_tlbiasid_p) {
     80 			armreg_icialluis_write(0);
     81 		} else {
     82 			armreg_iciallu_write(0);
     83 		}
     84 	}
     85 	dsb(sy);
     86 	isb();
     87 }
     88 
     89 void
     90 tlb_invalidate_globals(void)
     91 {
     92 	tlb_invalidate_all();
     93 }
     94 
     95 void
     96 tlb_invalidate_asids(tlb_asid_t lo, tlb_asid_t hi)
     97 {
     98 	const bool vivt_icache_p = arm_pcache.icache_type == CACHE_TYPE_VIVT;
     99 	dsb(sy);
    100 	if (arm_has_tlbiasid_p) {
    101 		for (; lo <= hi; lo++) {
    102 			if (arm_has_mpext_p) {
    103 				armreg_tlbiasidis_write(lo);
    104 			} else {
    105 				armreg_tlbiasid_write(lo);
    106 			}
    107 		}
    108 		dsb(sy);
    109 		isb();
    110 		if (__predict_false(vivt_icache_p)) {
    111 			if (arm_has_mpext_p) {
    112 				armreg_icialluis_write(0);
    113 			} else {
    114 				armreg_iciallu_write(0);
    115 			}
    116 		}
    117 	} else {
    118 		armreg_tlbiall_write(0);
    119 		isb();
    120 		if (__predict_false(vivt_icache_p)) {
    121 			armreg_iciallu_write(0);
    122 		}
    123 	}
    124 	isb();
    125 }
    126 
    127 void
    128 tlb_invalidate_addr(vaddr_t va, tlb_asid_t asid)
    129 {
    130 	dsb(sy);
    131 	va = trunc_page(va) | asid;
    132 	for (vaddr_t eva = va + PAGE_SIZE; va < eva; va += L2_S_SIZE) {
    133 		if (arm_has_mpext_p) {
    134 			armreg_tlbimvais_write(va);
    135 		} else {
    136 			armreg_tlbimva_write(va);
    137 		}
    138 	}
    139 	isb();
    140 }
    141 
    142 bool
    143 tlb_update_addr(vaddr_t va, tlb_asid_t asid, pt_entry_t pte, bool insert_p)
    144 {
    145 	tlb_invalidate_addr(va, asid);
    146 	return true;
    147 }
    148 
    149 #if !defined(MULTIPROCESSOR)
    150 static u_int
    151 tlb_cortex_a5_record_asids(u_long *mapp, tlb_asid_t asid_max)
    152 {
    153 	u_int nasids = 0;
    154 	for (size_t va_index = 0; va_index < 63; va_index++) {
    155 		for (size_t way = 0; way < 2; way++) {
    156 			armreg_tlbdataop_write(
    157 			     __SHIFTIN(way, ARM_TLBDATAOP_WAY)
    158 			     | __SHIFTIN(va_index, ARM_A5_TLBDATAOP_INDEX));
    159 			isb();
    160 			const uint64_t d = ((uint64_t) armreg_tlbdata1_read())
    161 			    | armreg_tlbdata0_read();
    162 			if (!(d & ARM_TLBDATA_VALID)
    163 			    || !(d & ARM_A5_TLBDATA_nG))
    164 				continue;
    165 
    166 			const tlb_asid_t asid = __SHIFTOUT(d,
    167 			    ARM_A5_TLBDATA_ASID);
    168 			const u_long mask = 1L << (asid & 31);
    169 			const size_t idx = asid >> 5;
    170 			if (mapp[idx] & mask)
    171 				continue;
    172 
    173 			mapp[idx] |= mask;
    174 			nasids++;
    175 		}
    176 	}
    177 	return nasids;
    178 }
    179 #endif
    180 
    181 #if !defined(MULTIPROCESSOR)
    182 static u_int
    183 tlb_cortex_a7_record_asids(u_long *mapp, tlb_asid_t asid_max)
    184 {
    185 	u_int nasids = 0;
    186 	for (size_t va_index = 0; va_index < 128; va_index++) {
    187 		for (size_t way = 0; way < 2; way++) {
    188 			armreg_tlbdataop_write(
    189 			     __SHIFTIN(way, ARM_TLBDATAOP_WAY)
    190 			     | __SHIFTIN(va_index, ARM_A7_TLBDATAOP_INDEX));
    191 			isb();
    192 			const uint32_t d0 = armreg_tlbdata0_read();
    193 			const uint32_t d1 = armreg_tlbdata1_read();
    194 			if (!(d0 & ARM_TLBDATA_VALID)
    195 			    || !(d1 & ARM_A7_TLBDATA1_nG))
    196 				continue;
    197 
    198 			const uint64_t d01 = ((uint64_t) d1)|d0;
    199 			const tlb_asid_t asid = __SHIFTOUT(d01,
    200 			    ARM_A7_TLBDATA01_ASID);
    201 			const u_long mask = 1L << (asid & 31);
    202 			const size_t idx = asid >> 5;
    203 			if (mapp[idx] & mask)
    204 				continue;
    205 
    206 			mapp[idx] |= mask;
    207 			nasids++;
    208 		}
    209 	}
    210 	return nasids;
    211 }
    212 #endif
    213 
    214 u_int
    215 tlb_record_asids(u_long *mapp, tlb_asid_t asid_max)
    216 {
    217 #ifndef MULTIPROCESSOR
    218 	if (CPU_ID_CORTEX_A5_P(curcpu()->ci_arm_cpuid))
    219 		return tlb_cortex_a5_record_asids(mapp, asid_max);
    220 	if (CPU_ID_CORTEX_A7_P(curcpu()->ci_arm_cpuid))
    221 		return tlb_cortex_a7_record_asids(mapp, asid_max);
    222 #endif /* MULTIPROCESSOR */
    223 #ifdef DIAGNOSTIC
    224 	mapp[0] = 0xfffffffe;
    225 	mapp[1] = 0xffffffff;
    226 	mapp[2] = 0xffffffff;
    227 	mapp[3] = 0xffffffff;
    228 	mapp[4] = 0xffffffff;
    229 	mapp[5] = 0xffffffff;
    230 	mapp[6] = 0xffffffff;
    231 	mapp[7] = 0xffffffff;
    232 #endif
    233 	return 255;
    234 }
    235 
    236 void
    237 tlb_walk(void *ctx, bool (*func)(void *, vaddr_t, tlb_asid_t, pt_entry_t))
    238 {
    239 	/* no way to view the TLB */
    240 }
    241