| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn10/ |
| amdgpu_dcn10_hw_sequencer.c | 2522 struct pipe_ctx *top_pipe_to_program = local in function:dcn10_apply_ctx_for_surface
2526 if (!top_pipe_to_program)
2529 tg = top_pipe_to_program->stream_res.tg;
2531 interdependent_update = top_pipe_to_program->plane_state &&
2532 top_pipe_to_program->plane_state->update_flags.bits.full_update;
2537 ASSERT(hws->funcs.did_underflow_occur(dc, top_pipe_to_program));
2542 dcn10_pipe_control_lock(dc, top_pipe_to_program, true);
2548 ASSERT(hws->funcs.did_underflow_occur(dc, top_pipe_to_program));
2552 hws->funcs.blank_pixel_data(dc, top_pipe_to_program, true);
2587 dcn10_program_all_pipe_in_tree(dc, top_pipe_to_program, context)
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/core/ |
| amdgpu_dc.c | 2160 struct pipe_ctx *top_pipe_to_program = NULL; local in function:commit_planes_for_stream
2232 top_pipe_to_program = pipe_ctx;
2280 * top_pipe_to_program is expected to never be NULL
2282 dc->hwss.pipe_control_lock(dc, top_pipe_to_program, true);
2326 dc->hwss.pipe_control_lock(dc, top_pipe_to_program, false);
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