| /src/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/engine/gr/ |
| nouveau_nvkm_engine_gr_gf117.c | 134 const u32 magicgpc918 = DIV_ROUND_UP(0x00800000, gr->tpc_total);
135 const u8 tile_nr = ALIGN(gr->tpc_total, 32);
140 for (data = 0, j = 0; j < 8 && i + j < gr->tpc_total; j++) {
151 gr->tpc_total);
|
| nouveau_nvkm_engine_gr_tu102.c | 62 const u32 magicgpc918 = DIV_ROUND_UP(0x00800000, gr->tpc_total);
63 const u8 tile_nr = ALIGN(gr->tpc_total, 64);
68 for (data = 0, j = 0; j < 8 && i + j < gr->tpc_total; j++) {
79 gr->tpc_total);
|
| nouveau_nvkm_engine_gr_ctxgv100.c | 75 u32 size = grctx->alpha_nr_max * gr->tpc_total;
125 nvkm_wr32(device, 0x418bb8, (gr->tpc_total << 8) |
136 nvkm_wr32(device, 0x41bfd0, (gr->tpc_total << 8) |
139 u8 v19 = (1 << (j + 0)) % gr->tpc_total;
140 u8 v20 = (1 << (j + 1)) % gr->tpc_total;
141 u8 v21 = (1 << (j + 2)) % gr->tpc_total;
142 u8 v22 = (1 << (j + 3)) % gr->tpc_total;
150 nvkm_wr32(device, 0x4078bc, (gr->tpc_total << 8) |
|
| nouveau_nvkm_engine_gr_gm200.c | 166 if (gr->gpc_nr == 2 && gr->tpc_total == 8) {
167 memcpy(gr->tile, gm200_gr_tile_map_2_8, gr->tpc_total);
170 if (gr->gpc_nr == 4 && gr->tpc_total == 16) {
171 memcpy(gr->tile, gm200_gr_tile_map_4_16, gr->tpc_total);
174 if (gr->gpc_nr == 6 && gr->tpc_total == 24) {
175 memcpy(gr->tile, gm200_gr_tile_map_6_24, gr->tpc_total);
|
| nouveau_nvkm_engine_gr_ctxgf117.c | 216 ntpcv = gr->tpc_total;
229 nvkm_wr32(device, 0x418bb8, (gr->tpc_total << 8) |
235 nvkm_wr32(device, 0x41bfd0, (gr->tpc_total << 8) |
242 nvkm_wr32(device, 0x4078bc, (gr->tpc_total << 8) |
257 const int b = mmio_vram(info, size * gr->tpc_total, (1 << s), false);
261 u32 ao = bo + grctx->attrib_nr_max * gr->tpc_total;
|
| nouveau_nvkm_engine_gr_ctxgk20a.c | 55 nvkm_wr32(device, 0x405b00, (gr->tpc_total << 8) | gr->gpc_nr);
|
| nouveau_nvkm_engine_gr_ctxgm20b.c | 52 nvkm_wr32(device, 0x405b00, (gr->tpc_total << 8) | gr->gpc_nr);
|
| nouveau_nvkm_engine_gr_ctxgp100.c | 58 u32 size = grctx->alpha_nr_max * gr->tpc_total;
104 const u32 dist_nr = DIV_ROUND_UP(gr->tpc_total, 4);
|
| nouveau_nvkm_engine_gr_ctxgm200.c | 54 const u32 dist_nr = DIV_ROUND_UP(gr->tpc_total, 4);
|
| nouveau_nvkm_engine_gr_ctxgp102.c | 54 u32 size = grctx->alpha_nr_max * gr->tpc_total;
|
| nouveau_nvkm_engine_gr_ctxgf100.c | 1076 const int b = mmio_vram(info, size * gr->tpc_total, (1 << s), false);
1133 ntpcv = gr->tpc_total;
1146 nvkm_wr32(device, 0x418bb8, (gr->tpc_total << 8) |
1152 nvkm_wr32(device, 0x419bd0, (gr->tpc_total << 8) |
1159 nvkm_wr32(device, 0x4078bc, (gr->tpc_total << 8) |
1283 u32 atarget = gf100_grctx_alpha_beta_map[gr->tpc_total][i];
1288 atarget = max_t(u32, gr->tpc_total * i / 32, 1);
|
| nouveau_nvkm_engine_gr_gf100.c | 1113 cfg |= (u32)gr->tpc_total << 8;
1883 switch (gr->tpc_total) {
1896 if (gr->tpc_total % primes[i]) {
1936 for (i = 0; i < gr->tpc_total;) {
1963 gr->tpc_total += gr->tpc_nr[i];
2207 const u32 magicgpc918 = DIV_ROUND_UP(0x00800000, gr->tpc_total);
2208 const u8 tile_nr = ALIGN(gr->tpc_total, 32);
2213 for (data = 0, j = 0; j < 8 && i + j < gr->tpc_total; j++) {
2224 gr->tpc_total);
|
| nouveau_nvkm_engine_gr_gk20a.c | 278 nvkm_wr32(device, 0x41ac94, (((1 << gr->tpc_total) - 1) & 0xff) << 16);
|
| nouveau_nvkm_engine_gr_ctxgk104.c | 931 nvkm_wr32(device, 0x405b00, (gr->tpc_total << 8) | gr->gpc_nr);
941 u32 atarget = max_t(u32, gr->tpc_total * i / 32, 1);
942 u32 btarget = gr->tpc_total - atarget;
|
| gf100.h | 118 u8 tpc_total; member in struct:gf100_gr
|
| nouveau_nvkm_engine_gr_ctxgf108.c | 749 const int b = mmio_vram(info, size * gr->tpc_total, (1 << s), false);
753 u32 ao = bo + grctx->attrib_nr_max * gr->tpc_total;
|
| nouveau_nvkm_engine_gr_ctxgm107.c | 922 const int b = mmio_vram(info, size * gr->tpc_total, (1 << s), false);
925 u32 ao = bo + grctx->attrib_nr_max * gr->tpc_total;
|
