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Searched refs:tpp_dg (Results 1 - 3 of 3) sorted by relevancy

/src/sys/arch/arm/nvidia/
tegra_pinmux.h	`50 } tpp_dg; member in union:tegra_pinmux_pins::__anon452d3cca010a`
tegra_pinmux.c	`183 cfg &= ~pin_def->tpp_dg.drvdn_mask; 184 cfg \|= __SHIFTIN(val, pin_def->tpp_dg.drvdn_mask); 187 cfg &= ~pin_def->tpp_dg.drvup_mask; 188 cfg \|= __SHIFTIN(val, pin_def->tpp_dg.drvup_mask); 191 cfg &= ~pin_def->tpp_dg.slwrf_mask; 192 cfg \|= __SHIFTIN(val, pin_def->tpp_dg.slwrf_mask); 195 cfg &= ~pin_def->tpp_dg.slwrr_mask; 196 cfg \|= __SHIFTIN(val, pin_def->tpp_dg.slwrr_mask);`
tegra210_pinmux.c	`54 .tpp_dg = { \`

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