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    Searched refs:ttbr1 (Results 1 - 3 of 3) sorted by relevancy

  /src/sys/external/mit/xen-include-public/dist/xen/include/public/
vm_event.h 206 uint64_t ttbr1; member in struct:vm_event_regs_arm
arch-arm.h 295 uint64_t ttbcr, ttbr0, ttbr1; member in struct:vcpu_guest_context
  /src/sys/arch/arm/include/
armreg.h 535 #define TTBCR_S_PD1 __BIT(5) // Don't use TTBR1
540 #define TTBCR_L_SH1 __BITS(29,28) // TTBR1 Shareability
541 #define TTBCR_L_ORGN1 __BITS(27,26) // TTBR1 Outer cacheability
542 #define TTBCR_L_IRGN1 __BITS(25,24) // TTBR1 inner cacheability
543 #define TTBCR_L_EPD1 __BIT(23) // Don't use TTBR1
544 #define TTBCR_L_A1 __BIT(22) // ASID is in TTBR1
545 #define TTBCR_L_T1SZ __BITS(18,16) // TTBR1 size offset
821 ARMREG_READ_INLINE(ttbr1, "p15,0,%0,c2,c0,1") /* Translation Table Base Register 1 */
822 ARMREG_WRITE_INLINE(ttbr1, "p15,0,%0,c2,c0,1") /* Translation Table Base Register 1 */

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