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    Searched refs:ucPostDiv (Results 1 - 8 of 8) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_atombios_crtc.c 445 if (args.v3.sOutput.ucPostDiv) {
448 amdgpu_crtc->pll_post_div = args.v3.sOutput.ucPostDiv;
618 args.v1.ucPostDiv = post_div;
628 args.v2.ucPostDiv = post_div;
638 args.v3.ucPostDiv = post_div;
655 args.v5.ucPostDiv = post_div;
685 args.v6.ucPostDiv = post_div;
amdgpu_atombios.c 1030 dividers->post_div = args.v3.ucPostDiv;
1050 dividers->post_div = args.v5.ucPostDiv;
1068 dividers->post_divider = dividers->post_div = args.v4.ucPostDiv;
1085 dividers->post_divider = args.v6_out.ulClock.ucPostDiv;
1122 mpll_param->post_div = args.ucPostDiv;
  /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/hwmgr/
amdgpu_ppatomctrl.c 275 (uint32_t)mpll_parameters.ucPostDiv;
318 (uint32_t)mpll_parameters.ulClock.ucPostDiv;
347 mpll_param->ulPostDiv = mpll_parameters.ulClock.ucPostDiv;
368 dividers->pll_post_divider = pll_parameters.ucPostDiv;
385 pll_patameters.ulClock.ucPostDiv = COMPUTE_GPUCLK_INPUT_FLAG_SCLK;
393 pll_patameters.ulClock.ucPostDiv;
422 pll_patameters.ulClock.ucPostDiv = COMPUTE_GPUCLK_INPUT_FLAG_SCLK;
454 pll_patameters.ulClock.ucPostDiv =
463 pll_patameters.ulClock.ucPostDiv;
1380 table->entry[i].ucPostdiv = psmu_info->asSclkFcwRangeEntry[i].ucPostdiv
    [all...]
  /src/sys/external/bsd/drm2/dist/drm/radeon/
radeon_atombios_crtc.c 748 if (args.v3.sOutput.ucPostDiv) {
751 radeon_crtc->pll_post_div = args.v3.sOutput.ucPostDiv;
864 args.v1.ucPostDiv = post_div;
874 args.v2.ucPostDiv = post_div;
884 args.v3.ucPostDiv = post_div;
901 args.v5.ucPostDiv = post_div;
930 args.v6.ucPostDiv = post_div;
atombios.h 416 UCHAR ucPostDiv; //return value
424 UCHAR ucPostDiv; //return post div to be written to register
469 UCHAR ucPostDiv; //Output Parameter
485 ULONG ucPostDiv:8; //return parameter: post divider which is used to program to register directly
489 ULONG ucPostDiv:8; //return parameter: post divider which is used to program to register directly
502 UCHAR ucPostDiv; //Output Parameter
525 COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4 ulClock; //Output Parameter: ucPostDiv=DFS divider
549 UCHAR ucPostDiv; //Output
1550 UCHAR ucPostDiv; // post divider
1570 UCHAR ucPostDiv; // post divider
    [all...]
radeon_atombios.c 2856 dividers->post_div = args.v1.ucPostDiv;
2870 dividers->post_div = args.v2.ucPostDiv;
2885 dividers->post_div = args.v3.ucPostDiv;
2905 dividers->post_div = args.v5.ucPostDiv;
2924 dividers->post_divider = dividers->post_div = args.v4.ucPostDiv;
2941 dividers->post_divider = args.v6_out.ulClock.ucPostDiv;
2978 mpll_param->post_div = args.ucPostDiv;
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/bios/
amdgpu_command_table.c 967 allocation.sPCLKInput.ucPostDiv =
1038 clk.sPCLKInput.ucPostDiv =
1114 clk.sPCLKInput.ucPostDiv =
1526 bp_params->pixel_clock_post_divider = params.sOutput.ucPostDiv;
  /src/sys/external/bsd/drm2/dist/drm/amd/include/
atombios.h 446 UCHAR ucPostDiv; //return value
454 UCHAR ucPostDiv; //return post div to be written to register
503 UCHAR ucPostDiv; //Output Parameter
519 ULONG ucPostDiv:8; //return parameter: post divider which is used to program to register directly
523 ULONG ucPostDiv:8; //return parameter: post divider which is used to program to register directly
536 UCHAR ucPostDiv; //Output Parameter
560 COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4 ulClock; //Output Parameter: ucPostDiv=DFS divider
584 COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4 ulClock; //Output Parameter: ucPostDiv=DFS divider
611 UCHAR ucPostDiv; //Output
1825 UCHAR ucPostDiv; // post divide
    [all...]

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