amdgpu_dcn20_resource.c | 3208 struct pp_smu_nv_clock_table *max_clocks, unsigned int *uclk_states, unsigned int num_states) 3234 calculated_states[i].dram_speed_mts = uclk_states[i] * 16 / 1000; 3237 min_fclk_required_by_uclk = mul_u64_u32_shr(BIT_ULL(32) * 1080 / 1000000, uclk_states[i], 32); 3447 unsigned int uclk_states[8] = {0}; local in function:init_soc_bounding_box 3455 (&pool->base.pp_smu->nv_funcs.pp_smu, uclk_states, &num_states); 3471 dcn20_update_bounding_box(dc, loaded_bb, &max_clocks, uclk_states, num_states);
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