1 /* $NetBSD: pic_uic.c,v 1.10 2026/06/13 20:16:23 rkujawa Exp $ */ 2 3 /* 4 * Copyright 2002 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Eduardo Horvath and Simon Burge for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 #include <sys/cdefs.h> 39 __KERNEL_RCSID(0, "$NetBSD: pic_uic.c,v 1.10 2026/06/13 20:16:23 rkujawa Exp $"); 40 41 #ifdef _KERNEL_OPT 42 #include "opt_ppcarch.h" 43 #include "opt_uic.h" 44 #endif 45 46 #include <sys/param.h> 47 #include <sys/kernel.h> 48 #include <sys/evcnt.h> 49 #include <sys/cpu.h> 50 51 #include <machine/intr.h> 52 #include <machine/psl.h> 53 54 #include <powerpc/spr.h> 55 #include <powerpc/ibm4xx/spr.h> 56 #include <powerpc/ibm4xx/cpu.h> 57 58 #include <powerpc/pic/picvar.h> 59 60 /* 61 * Number of interrupts (hard + soft), irq number legality test, 62 * mapping of irq number to mask and a way to pick irq number 63 * off a mask of active intrs. 64 */ 65 #define IRQ_TO_MASK(irq) (0x80000000UL >> ((irq) & 0x1f)) 66 #define IRQ_OF_MASK(mask) __builtin_clz(mask) 67 68 static void uic_enable_irq(struct pic_ops *, int, int); 69 static void uic_disable_irq(struct pic_ops *, int); 70 static int uic_get_irq(struct pic_ops *, int); 71 static void uic_ack_irq(struct pic_ops *, int); 72 static void uic_establish_irq(struct pic_ops *, int, int, int); 73 74 struct uic { 75 uint32_t uic_intr_enable; /* cached intr enable mask */ 76 #ifdef PPC_IBM403 77 /* 78 * Not clearly documented in reference manual, but DCR_EXISR 79 * register is not updated immediately after some bits are 80 * cleared by mtdcr, no matter whether sync (= eieio) and/or 81 * isync are issued. 82 * 83 * Therefore, we have to manage our own status mask in the 84 * interrupt handler; see uic_{ack,get}_irq() for more details. 85 * This is what we did in obsoleted powerpc/ibm4xx/intr.c. 86 */ 87 uint32_t uic_intr_status; 88 #endif 89 uint32_t (*uic_mf_intr_status)(void); 90 uint32_t (*uic_mf_intr_enable)(void); 91 void (*uic_mt_intr_enable)(uint32_t); 92 void (*uic_mt_intr_ack)(uint32_t); 93 }; 94 95 /* 96 * Platform specific code may override any of the above. 97 */ 98 #ifdef PPC_IBM403 99 100 #include <powerpc/ibm4xx/dcr403cgx.h> 101 102 static uint32_t 103 uic403_mfdcr_intr_status(void) 104 { 105 return mfdcr(DCR_EXISR); 106 } 107 108 static uint32_t 109 uic403_mfdcr_intr_enable(void) 110 { 111 return mfdcr(DCR_EXIER); 112 } 113 114 static void 115 uic403_mtdcr_intr_ack(uint32_t v) 116 { 117 mtdcr(DCR_EXISR, v); 118 } 119 120 static void 121 uic403_mtdcr_intr_enable(uint32_t v) 122 { 123 mtdcr(DCR_EXIER, v); 124 } 125 126 struct uic uic403 = { 127 .uic_intr_enable = 0, 128 .uic_mf_intr_status = uic403_mfdcr_intr_status, 129 .uic_mf_intr_enable = uic403_mfdcr_intr_enable, 130 .uic_mt_intr_enable = uic403_mtdcr_intr_enable, 131 .uic_mt_intr_ack = uic403_mtdcr_intr_ack, 132 }; 133 134 struct pic_ops pic_uic403 = { 135 .pic_cookie = &uic403, 136 .pic_numintrs = 32, 137 .pic_enable_irq = uic_enable_irq, 138 .pic_reenable_irq = uic_enable_irq, 139 .pic_disable_irq = uic_disable_irq, 140 .pic_establish_irq = uic_establish_irq, 141 .pic_get_irq = uic_get_irq, 142 .pic_ack_irq = uic_ack_irq, 143 .pic_finish_setup = NULL, 144 .pic_name = "uic0" 145 }; 146 147 #else /* Generic 405/440/460 Universal Interrupt Controller */ 148 149 #include <powerpc/ibm4xx/dcr4xx.h> 150 151 #include "opt_uic.h" 152 153 /* 405EP/405GP/405GPr/Virtex-4 */ 154 155 static uint32_t 156 uic0_mfdcr_intr_status(void) 157 { 158 return mfdcr(DCR_UIC0_BASE + DCR_UIC_MSR); 159 } 160 161 static uint32_t 162 uic0_mfdcr_intr_enable(void) 163 { 164 return mfdcr(DCR_UIC0_BASE + DCR_UIC_ER); 165 } 166 167 static void 168 uic0_mtdcr_intr_ack(uint32_t v) 169 { 170 mtdcr(DCR_UIC0_BASE + DCR_UIC_SR, v); 171 } 172 173 static void 174 uic0_mtdcr_intr_enable(uint32_t v) 175 { 176 mtdcr(DCR_UIC0_BASE + DCR_UIC_ER, v); 177 } 178 179 struct uic uic0 = { 180 .uic_intr_enable = 0, 181 .uic_mf_intr_status = uic0_mfdcr_intr_status, 182 .uic_mf_intr_enable = uic0_mfdcr_intr_enable, 183 .uic_mt_intr_enable = uic0_mtdcr_intr_enable, 184 .uic_mt_intr_ack = uic0_mtdcr_intr_ack, 185 }; 186 187 struct pic_ops pic_uic0 = { 188 .pic_cookie = &uic0, 189 .pic_numintrs = 32, 190 .pic_enable_irq = uic_enable_irq, 191 .pic_reenable_irq = uic_enable_irq, 192 .pic_disable_irq = uic_disable_irq, 193 .pic_establish_irq = uic_establish_irq, 194 .pic_get_irq = uic_get_irq, 195 .pic_ack_irq = uic_ack_irq, 196 .pic_finish_setup = NULL, 197 .pic_name = "uic0" 198 }; 199 200 #ifdef MULTIUIC 201 202 /* 203 * Cascade inputs on UIC0. The defaults match the 405EX; SoCs with 204 * different wiring should override via options in the kernel config. 205 */ 206 #ifndef UIC1_CASCADE_IRQ 207 #define UIC1_CASCADE_IRQ 30 208 #endif 209 #ifndef UIC2_CASCADE_IRQ 210 #define UIC2_CASCADE_IRQ 28 211 #endif 212 213 static uint32_t 214 uic1_mfdcr_intr_status(void) 215 { 216 return mfdcr(DCR_UIC1_BASE + DCR_UIC_MSR); 217 } 218 219 static uint32_t 220 uic1_mfdcr_intr_enable(void) 221 { 222 return mfdcr(DCR_UIC1_BASE + DCR_UIC_ER); 223 } 224 225 static void 226 uic1_mtdcr_intr_ack(uint32_t v) 227 { 228 mtdcr(DCR_UIC1_BASE + DCR_UIC_SR, v); 229 } 230 231 static void 232 uic1_mtdcr_intr_enable(uint32_t v) 233 { 234 mtdcr(DCR_UIC1_BASE + DCR_UIC_ER, v); 235 } 236 237 extern struct pic_ops pic_uic1; 238 239 static void 240 uic1_finish_setup(struct pic_ops *pic) 241 { 242 intr_establish_xname(UIC1_CASCADE_IRQ, IST_LEVEL, IPL_HIGH, 243 pic_handle_intr, &pic_uic1, "uic1"); 244 } 245 246 struct uic uic1 = { 247 .uic_intr_enable = 0, 248 .uic_mf_intr_status = uic1_mfdcr_intr_status, 249 .uic_mf_intr_enable = uic1_mfdcr_intr_enable, 250 .uic_mt_intr_enable = uic1_mtdcr_intr_enable, 251 .uic_mt_intr_ack = uic1_mtdcr_intr_ack, 252 }; 253 254 struct pic_ops pic_uic1 = { 255 .pic_cookie = &uic1, 256 .pic_numintrs = 32, 257 .pic_enable_irq = uic_enable_irq, 258 .pic_reenable_irq = uic_enable_irq, 259 .pic_disable_irq = uic_disable_irq, 260 .pic_establish_irq = uic_establish_irq, 261 .pic_get_irq = uic_get_irq, 262 .pic_ack_irq = uic_ack_irq, 263 .pic_finish_setup = uic1_finish_setup, 264 .pic_name = "uic1" 265 }; 266 267 static uint32_t 268 uic2_mfdcr_intr_status(void) 269 { 270 return mfdcr(DCR_UIC2_BASE + DCR_UIC_MSR); 271 } 272 273 static uint32_t 274 uic2_mfdcr_intr_enable(void) 275 { 276 return mfdcr(DCR_UIC2_BASE + DCR_UIC_ER); 277 } 278 279 static void 280 uic2_mtdcr_intr_ack(uint32_t v) 281 { 282 mtdcr(DCR_UIC2_BASE + DCR_UIC_SR, v); 283 } 284 285 static void 286 uic2_mtdcr_intr_enable(uint32_t v) 287 { 288 mtdcr(DCR_UIC2_BASE + DCR_UIC_ER, v); 289 } 290 291 extern struct pic_ops pic_uic2; 292 293 static void 294 uic2_finish_setup(struct pic_ops *pic) 295 { 296 intr_establish_xname(UIC2_CASCADE_IRQ, IST_LEVEL, IPL_HIGH, 297 pic_handle_intr, &pic_uic2, "uic2"); 298 } 299 300 static struct uic uic2 = { 301 .uic_intr_enable = 0, 302 .uic_mf_intr_status = uic2_mfdcr_intr_status, 303 .uic_mf_intr_enable = uic2_mfdcr_intr_enable, 304 .uic_mt_intr_enable = uic2_mtdcr_intr_enable, 305 .uic_mt_intr_ack = uic2_mtdcr_intr_ack, 306 }; 307 308 struct pic_ops pic_uic2 = { 309 .pic_cookie = &uic2, 310 .pic_numintrs = 32, 311 .pic_enable_irq = uic_enable_irq, 312 .pic_reenable_irq = uic_enable_irq, 313 .pic_disable_irq = uic_disable_irq, 314 .pic_establish_irq = uic_establish_irq, 315 .pic_get_irq = uic_get_irq, 316 .pic_ack_irq = uic_ack_irq, 317 .pic_finish_setup = uic2_finish_setup, 318 .pic_name = "uic2" 319 }; 320 321 #ifdef UIC3_CASCADE_IRQ 322 323 static uint32_t 324 uic3_mfdcr_intr_status(void) 325 { 326 return mfdcr(DCR_UIC3_BASE + DCR_UIC_MSR); 327 } 328 329 static uint32_t 330 uic3_mfdcr_intr_enable(void) 331 { 332 return mfdcr(DCR_UIC3_BASE + DCR_UIC_ER); 333 } 334 335 static void 336 uic3_mtdcr_intr_ack(uint32_t v) 337 { 338 mtdcr(DCR_UIC3_BASE + DCR_UIC_SR, v); 339 } 340 341 static void 342 uic3_mtdcr_intr_enable(uint32_t v) 343 { 344 mtdcr(DCR_UIC3_BASE + DCR_UIC_ER, v); 345 } 346 347 extern struct pic_ops pic_uic3; 348 349 static void 350 uic3_finish_setup(struct pic_ops *pic) 351 { 352 intr_establish_xname(UIC3_CASCADE_IRQ, IST_LEVEL, IPL_HIGH, 353 pic_handle_intr, &pic_uic3, "uic3"); 354 } 355 356 static struct uic uic3 = { 357 .uic_intr_enable = 0, 358 .uic_mf_intr_status = uic3_mfdcr_intr_status, 359 .uic_mf_intr_enable = uic3_mfdcr_intr_enable, 360 .uic_mt_intr_enable = uic3_mtdcr_intr_enable, 361 .uic_mt_intr_ack = uic3_mtdcr_intr_ack, 362 }; 363 364 struct pic_ops pic_uic3 = { 365 .pic_cookie = &uic3, 366 .pic_numintrs = 32, 367 .pic_enable_irq = uic_enable_irq, 368 .pic_reenable_irq = uic_enable_irq, 369 .pic_disable_irq = uic_disable_irq, 370 .pic_establish_irq = uic_establish_irq, 371 .pic_get_irq = uic_get_irq, 372 .pic_ack_irq = uic_ack_irq, 373 .pic_finish_setup = uic3_finish_setup, 374 .pic_name = "uic3" 375 }; 376 377 #endif /* UIC3_CASCADE_IRQ */ 378 379 #endif /* MULTIUIC */ 380 #endif /* !PPC_IBM403 */ 381 382 /* 383 * Set up interrupt mapping array. 384 */ 385 void 386 intr_init(void) 387 { 388 #ifdef PPC_IBM403 389 struct pic_ops * const pic = &pic_uic403; 390 #else 391 struct pic_ops * const pic = &pic_uic0; 392 #endif 393 struct uic * const uic = pic->pic_cookie; 394 395 uic->uic_mt_intr_enable(0x00000000); /* mask all */ 396 uic->uic_mt_intr_ack(0xffffffff); /* acknowledge all */ 397 398 pic_add(pic); 399 } 400 401 static void 402 uic_disable_irq(struct pic_ops *pic, int irq) 403 { 404 struct uic * const uic = pic->pic_cookie; 405 const uint32_t irqmask = IRQ_TO_MASK(irq); 406 if ((uic->uic_intr_enable & irqmask) == 0) 407 return; 408 uic->uic_intr_enable ^= irqmask; 409 (*uic->uic_mt_intr_enable)(uic->uic_intr_enable); 410 #ifdef IRQ_DEBUG 411 printf("%s: %s: irq=%d, mask=%08x\n", __func__, 412 pic->pic_name, irq, irqmask); 413 #endif 414 } 415 416 static void 417 uic_enable_irq(struct pic_ops *pic, int irq, int type) 418 { 419 struct uic * const uic = pic->pic_cookie; 420 const uint32_t irqmask = IRQ_TO_MASK(irq); 421 if ((uic->uic_intr_enable & irqmask) != 0) 422 return; 423 uic->uic_intr_enable ^= irqmask; 424 (*uic->uic_mt_intr_enable)(uic->uic_intr_enable); 425 #ifdef IRQ_DEBUG 426 printf("%s: %s: irq=%d, mask=%08x\n", __func__, 427 pic->pic_name, irq, irqmask); 428 #endif 429 } 430 431 static void 432 uic_ack_irq(struct pic_ops *pic, int irq) 433 { 434 struct uic * const uic = pic->pic_cookie; 435 const uint32_t irqmask = IRQ_TO_MASK(irq); 436 437 #ifdef PPC_IBM403 438 uic->uic_intr_status &= ~irqmask; 439 #endif 440 441 (*uic->uic_mt_intr_ack)(irqmask); 442 } 443 444 static int 445 uic_get_irq(struct pic_ops *pic, int req) 446 { 447 struct uic * const uic = pic->pic_cookie; 448 449 #ifdef PPC_IBM403 450 if (req == PIC_GET_IRQ) 451 uic->uic_intr_status = (*uic->uic_mf_intr_status)(); 452 const uint32_t irqmask = uic->uic_intr_status; 453 #else 454 const uint32_t irqmask = (*uic->uic_mf_intr_status)(); 455 #endif 456 457 if (irqmask == 0) 458 return 255; 459 return IRQ_OF_MASK(irqmask); 460 } 461 462 /* 463 * Register an interrupt handler. 464 */ 465 static void 466 uic_establish_irq(struct pic_ops *pic, int irq, int type, int ipl) 467 { 468 } 469
Indexes created Tue Jul 07 00:25:39 UTC 2026