HomeSort by: relevance | last modified time | path
    Searched refs:umc (Results 1 - 6 of 6) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_umc.c 42 if (!adev->umc.ras_if) {
43 adev->umc.ras_if =
45 if (!adev->umc.ras_if)
47 adev->umc.ras_if->block = AMDGPU_RAS_BLOCK__UMC;
48 adev->umc.ras_if->type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE;
49 adev->umc.ras_if->sub_block_index = 0;
50 strcpy(adev->umc.ras_if->name, "umc");
52 ih_info.head = fs_info.head = *adev->umc.ras_if;
54 r = amdgpu_ras_late_init(adev, adev->umc.ras_if
    [all...]
amdgpu_umc_v6_1.c 34 #include "umc/umc_6_1_1_offset.h"
35 #include "umc/umc_6_1_1_sh_mask.h"
36 #include "umc/umc_6_1_2_offset.h"
50 #define LOOP_UMC_INST(umc_inst) for ((umc_inst) = 0; (umc_inst) < adev->umc.umc_inst_num; (umc_inst)++)
51 #define LOOP_UMC_CH_INST(ch_inst) for ((ch_inst) = 0; (ch_inst) < adev->umc.channel_inst_num; (ch_inst)++)
90 return adev->umc.channel_offs*ch_inst + UMC_6_INST_DIST*umc_inst;
103 /* UMC 6_1_2 registers */
105 SOC15_REG_OFFSET(UMC, 0, mmUMCCH0_0_EccErrCntSel_ARCT);
107 SOC15_REG_OFFSET(UMC, 0, mmUMCCH0_0_EccErrCnt_ARCT);
109 SOC15_REG_OFFSET(UMC, 0, mmMCA_UMC_UMC0_MCUMC_STATUST0_ARCT)
    [all...]
amdgpu_gmc_v9_0.c 53 #include "umc/umc_6_0_sh_mask.h"
801 adev->umc.funcs = &umc_v6_0_funcs;
804 adev->umc.max_ras_err_cnt_per_query = UMC_V6_1_TOTAL_CHANNEL_NUM;
805 adev->umc.channel_inst_num = UMC_V6_1_CHANNEL_INSTANCE_NUM;
806 adev->umc.umc_inst_num = UMC_V6_1_UMC_INSTANCE_NUM;
807 adev->umc.channel_offs = UMC_V6_1_PER_CHANNEL_OFFSET_VG20;
808 adev->umc.channel_idx_tbl = &umc_v6_1_channel_idx_tbl[0][0];
809 adev->umc.funcs = &umc_v6_1_funcs;
812 adev->umc.max_ras_err_cnt_per_query = UMC_V6_1_TOTAL_CHANNEL_NUM;
813 adev->umc.channel_inst_num = UMC_V6_1_CHANNEL_INSTANCE_NUM
    [all...]
amdgpu_gmc.c 339 if (adev->umc.funcs && adev->umc.funcs->ras_late_init) {
340 r = adev->umc.funcs->ras_late_init(adev);
amdgpu_ras.c 52 "umc",
255 * block: umc, sdma, gfx, .........
267 * echo inject umc ue 0x0 0x0 0x0 > /sys/kernel/debug/dri/0/ras/ras_ctrl
268 * echo inject umc ce 0 0 0 > /sys/kernel/debug/dri/0/ras/ras_ctrl
269 * echo disable umc > /sys/kernel/debug/dri/0/ras/ras_ctrl
313 /* umc ce/ue error injection for a bad page is not allowed */
707 if (adev->umc.funcs->query_ras_error_count)
708 adev->umc.funcs->query_ras_error_count(adev, &err_data);
709 /* umc query_ras_error_address is also responsible for clearing
712 if (adev->umc.funcs->query_ras_error_address
    [all...]
amdgpu.h 930 /* UMC */
931 struct amdgpu_umc umc; member in struct:amdgpu_device

Completed in 18 milliseconds