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Searched refs:underlay_maximum_width_efficient_for_tiling (Results 1 - 3 of 3) sorted by relevancy

/src/sys/external/bsd/drm2/dist/drm/amd/display/dc/inc/
dce_calcs.h	`175 struct bw_fixed underlay_maximum_width_efficient_for_tiling; member in struct:bw_calcs_dceip`
/src/sys/external/bsd/drm2/dist/drm/amd/display/dc/calcs/
calcs_logger.h	`98 DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] underlay_maximum_width_efficient_for_tiling: %d", 99 bw_fixed_to_int(dceip->underlay_maximum_width_efficient_for_tiling));`
amdgpu_dce_calcs.c	`677 data->underlay_maximum_source_efficient_for_tiling = dceip->underlay_maximum_width_efficient_for_tiling; 2133 dceip.underlay_maximum_width_efficient_for_tiling = 2249 dceip.underlay_maximum_width_efficient_for_tiling = 2365 dceip.underlay_maximum_width_efficient_for_tiling = 2481 dceip.underlay_maximum_width_efficient_for_tiling = 2594 dceip.underlay_maximum_width_efficient_for_tiling = 2707 dceip.underlay_maximum_width_efficient_for_tiling =`

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