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    Searched refs:upper_32_bits (Results 1 - 25 of 177) sorted by relevancy

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  /src/sys/external/bsd/drm2/dist/drm/amd/amdkfd/
kfd_packet_manager_v9.c 63 packet->sq_shader_tba_hi = upper_32_bits(qpd->tba_addr >> 8)
67 packet->sq_shader_tma_hi = upper_32_bits(qpd->tma_addr >> 8);
71 packet->gds_addr_hi = upper_32_bits(qpd->gds_context_area);
76 upper_32_bits(vm_page_table_base_addr);
114 packet->ib_base_hi = upper_32_bits(ib);
139 packet->gws_mask_hi = upper_32_bits(res->gws_mask);
142 packet->queue_mask_hi = upper_32_bits(res->queue_mask);
203 upper_32_bits(q->gart_mqd_addr);
209 upper_32_bits((uint64_t)q->properties.write_ptr);
308 packet->addr_hi = upper_32_bits((uint64_t)fence_address)
    [all...]
kfd_packet_manager_vi.c 74 packet->gds_addr_hi = upper_32_bits(qpd->gds_context_area);
113 packet->bitfields3.ib_base_hi = upper_32_bits(ib);
138 packet->gws_mask_hi = upper_32_bits(res->gws_mask);
141 packet->queue_mask_hi = upper_32_bits(res->queue_mask);
193 upper_32_bits(q->gart_mqd_addr);
199 upper_32_bits((uint64_t)q->properties.write_ptr);
287 packet->addr_hi = upper_32_bits((uint64_t)fence_address);
289 packet->data_hi = upper_32_bits((uint64_t)fence_value);
317 packet->address_hi = upper_32_bits(gpu_addr);
kfd_mqd_manager_vi.c 121 m->cp_mqd_base_addr_hi = upper_32_bits(addr);
135 m->compute_tba_hi = upper_32_bits(q->tba_addr >> 8);
137 m->compute_tma_hi = upper_32_bits(q->tma_addr >> 8);
148 upper_32_bits(q->ctx_save_restore_area_address);
189 m->cp_hqd_pq_base_hi = upper_32_bits((uint64_t)q->queue_address >> 8);
192 m->cp_hqd_pq_rptr_report_addr_hi = upper_32_bits((uint64_t)q->read_ptr);
194 m->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits((uint64_t)q->write_ptr);
221 upper_32_bits(q->eop_ring_buffer_address >> 8);
362 m->sdmax_rlcx_rb_base_hi = upper_32_bits(q->queue_address >> 8);
364 m->sdmax_rlcx_rb_rptr_addr_hi = upper_32_bits((uint64_t)q->read_ptr)
    [all...]
kfd_mqd_manager_v10.c 117 m->cp_mqd_base_addr_hi = upper_32_bits(addr);
134 upper_32_bits(q->ctx_save_restore_area_address);
182 m->cp_hqd_pq_base_hi = upper_32_bits((uint64_t)q->queue_address >> 8);
185 m->cp_hqd_pq_rptr_report_addr_hi = upper_32_bits((uint64_t)q->read_ptr);
187 m->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits((uint64_t)q->write_ptr);
209 upper_32_bits(q->eop_ring_buffer_address >> 8);
339 m->sdmax_rlcx_rb_base_hi = upper_32_bits(q->queue_address >> 8);
341 m->sdmax_rlcx_rb_rptr_addr_hi = upper_32_bits((uint64_t)q->read_ptr);
kfd_mqd_manager_v9.c 152 m->cp_mqd_base_addr_hi = upper_32_bits(addr);
174 upper_32_bits(q->ctx_save_restore_area_address);
219 m->cp_hqd_pq_base_hi = upper_32_bits((uint64_t)q->queue_address >> 8);
222 m->cp_hqd_pq_rptr_report_addr_hi = upper_32_bits((uint64_t)q->read_ptr);
224 m->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits((uint64_t)q->write_ptr);
248 upper_32_bits(q->eop_ring_buffer_address >> 8);
382 m->sdmax_rlcx_rb_base_hi = upper_32_bits(q->queue_address >> 8);
384 m->sdmax_rlcx_rb_rptr_addr_hi = upper_32_bits((uint64_t)q->read_ptr);
kfd_mqd_manager_cik.c 121 m->cp_mqd_base_addr_hi = upper_32_bits(addr);
212 m->cp_hqd_pq_base_hi = upper_32_bits((uint64_t)q->queue_address >> 8);
214 m->cp_hqd_pq_rptr_report_addr_hi = upper_32_bits((uint64_t)q->read_ptr);
253 m->sdma_rlc_rb_base_hi = upper_32_bits(q->queue_address >> 8);
255 m->sdma_rlc_rb_rptr_addr_hi = upper_32_bits((uint64_t)q->read_ptr);
335 m->cp_hqd_pq_base_hi = upper_32_bits((uint64_t)q->queue_address >> 8);
337 m->cp_hqd_pq_rptr_report_addr_hi = upper_32_bits((uint64_t)q->read_ptr);
  /src/sys/external/bsd/drm2/dist/drm/i915/gt/
intel_lrc_reg.h 40 (reg_state__)[CTX_PDP ## n ## _UDW] = upper_32_bits(addr__); \
47 (reg_state__)[CTX_PDP0_UDW] = upper_32_bits(addr__); \
  /src/sys/external/bsd/drm2/dist/drm/nouveau/
nouveau_nvc0_fence.c 42 OUT_RING (chan, upper_32_bits(virtual));
58 OUT_RING (chan, upper_32_bits(virtual));
  /src/sys/external/bsd/drm2/dist/drm/radeon/
radeon_si_dma.c 88 ib->ptr[ib->length_dw++] = upper_32_bits(pe) & 0xff;
89 ib->ptr[ib->length_dw++] = upper_32_bits(src) & 0xff;
127 ib->ptr[ib->length_dw++] = upper_32_bits(pe) & 0xff;
139 ib->ptr[ib->length_dw++] = upper_32_bits(value);
179 ib->ptr[ib->length_dw++] = upper_32_bits(pe) & 0xff;
183 ib->ptr[ib->length_dw++] = upper_32_bits(value);
271 radeon_ring_write(ring, upper_32_bits(dst_offset) & 0xff);
272 radeon_ring_write(ring, upper_32_bits(src_offset) & 0xff);
radeon_evergreen_dma.c 54 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff));
84 radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xff);
95 radeon_ring_write(ring, (ib->length_dw << 12) | (upper_32_bits(ib->gpu_addr) & 0xFF));
148 radeon_ring_write(ring, upper_32_bits(dst_offset) & 0xff);
149 radeon_ring_write(ring, upper_32_bits(src_offset) & 0xff);
radeon_ni_dma.c 140 radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xff);
151 radeon_ring_write(ring, (ib->length_dw << 12) | (upper_32_bits(ib->gpu_addr) & 0xFF));
228 upper_32_bits(rdev->wb.gpu_addr + wb_offset) & 0xFF);
336 ib->ptr[ib->length_dw++] = upper_32_bits(pe) & 0xff;
337 ib->ptr[ib->length_dw++] = upper_32_bits(src) & 0xff;
376 ib->ptr[ib->length_dw++] = upper_32_bits(pe) & 0xff;
388 ib->ptr[ib->length_dw++] = upper_32_bits(value);
428 ib->ptr[ib->length_dw++] = upper_32_bits(pe) & 0xff;
432 ib->ptr[ib->length_dw++] = upper_32_bits(value);
radeon_rv770_dma.c 82 radeon_ring_write(ring, upper_32_bits(dst_offset) & 0xff);
83 radeon_ring_write(ring, upper_32_bits(src_offset) & 0xff);
radeon_r600_dma.c 149 upper_32_bits(rdev->wb.gpu_addr + R600_WB_DMA_RPTR_OFFSET) & 0xFF);
260 radeon_ring_write(ring, upper_32_bits(gpu_addr) & 0xff);
300 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff));
327 radeon_ring_write(ring, upper_32_bits(addr) & 0xff);
365 ib.ptr[2] = upper_32_bits(gpu_addr) & 0xff;
420 radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xff);
431 radeon_ring_write(ring, (ib->length_dw << 16) | (upper_32_bits(ib->gpu_addr) & 0xFF));
483 radeon_ring_write(ring, (((upper_32_bits(dst_offset) & 0xff) << 16) |
484 (upper_32_bits(src_offset) & 0xff)));
radeon_cik_sdma.c 151 radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr));
161 radeon_ring_write(ring, upper_32_bits(ib->gpu_addr));
214 radeon_ring_write(ring, upper_32_bits(addr));
243 radeon_ring_write(ring, upper_32_bits(addr));
406 upper_32_bits(rdev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF);
620 radeon_ring_write(ring, upper_32_bits(src_offset));
622 radeon_ring_write(ring, upper_32_bits(dst_offset));
676 radeon_ring_write(ring, upper_32_bits(gpu_addr));
734 ib.ptr[2] = upper_32_bits(gpu_addr);
823 ib->ptr[ib->length_dw++] = upper_32_bits(src)
    [all...]
  /src/sys/external/bsd/drm2/dist/drm/i915/selftests/
i915_random.h 51 return upper_32_bits(mul_u32_u32(prandom_u32_state(state), ep_ro));
  /src/sys/external/bsd/drm2/dist/drm/lib/
drm_random.c 17 return upper_32_bits((u64)prandom_u32_state(state) * ep_ro);
  /src/sys/external/bsd/drm2/dist/drm/nouveau/include/nvkm/core/
os.h 36 iowrite32_native(upper_32_bits(_v), &_p[1]); \
  /src/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/subdev/pmu/
nouveau_nvkm_subdev_pmu_gm20b.c 89 hdr.code_dma_base1 = upper_32_bits((addr + adjust) >> 8);
92 hdr.data_dma_base1 = upper_32_bits((addr + adjust) >> 8);
95 hdr.overlay_dma_base1 = upper_32_bits((addr + adjust) << 8);
119 .code_dma_base1 = upper_32_bits(code),
120 .data_dma_base1 = upper_32_bits(data),
121 .overlay_dma_base1 = upper_32_bits(code),
  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_sdma_v2_4.c 270 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
321 amdgpu_ring_write(ring, upper_32_bits(addr));
329 amdgpu_ring_write(ring, upper_32_bits(addr));
330 amdgpu_ring_write(ring, upper_32_bits(seq));
462 upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF);
577 amdgpu_ring_write(ring, upper_32_bits(gpu_addr));
630 ib.ptr[2] = upper_32_bits(gpu_addr);
684 ib->ptr[ib->length_dw++] = upper_32_bits(src);
686 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
709 ib->ptr[ib->length_dw++] = upper_32_bits(pe)
    [all...]
amdgpu_si_dma.c 81 amdgpu_ring_write(ring, (ib->length_dw << 12) | (upper_32_bits(ib->gpu_addr) & 0xFF));
103 amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xff));
110 amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xff));
111 amdgpu_ring_write(ring, upper_32_bits(seq));
164 WREG32(DMA_RB_RPTR_ADDR_HI + sdma_offsets[i], upper_32_bits(rptr_addr) & 0xFF);
230 amdgpu_ring_write(ring, upper_32_bits(gpu_addr) & 0xff);
281 ib.ptr[2] = upper_32_bits(gpu_addr) & 0xff;
329 ib->ptr[ib->length_dw++] = upper_32_bits(pe) & 0xff;
330 ib->ptr[ib->length_dw++] = upper_32_bits(src) & 0xff;
352 ib->ptr[ib->length_dw++] = upper_32_bits(pe)
    [all...]
amdgpu_sdma_v5_0.c 245 amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr));
338 "upper_32_bits(ring->wptr) << 2 == 0x%08x\n",
341 upper_32_bits(ring->wptr << 2));
344 adev->wb.wb[ring->wptr_offs + 1] = upper_32_bits(ring->wptr << 2);
355 upper_32_bits(ring->wptr << 2));
359 upper_32_bits(ring->wptr << 2));
406 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
409 amdgpu_ring_write(ring, upper_32_bits(csa_mc_addr));
462 amdgpu_ring_write(ring, upper_32_bits(addr));
473 amdgpu_ring_write(ring, upper_32_bits(addr))
    [all...]
  /src/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/engine/dma/
nouveau_nvkm_engine_dma_usergv100.c 57 nvkm_wo32(*pgpuobj, 0x08, upper_32_bits(start));
59 nvkm_wo32(*pgpuobj, 0x10, upper_32_bits(limit));
  /src/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/engine/fifo/
nouveau_nvkm_engine_fifo_dmag84.c 74 nvkm_wo32(chan->ramfc, 0x0c, upper_32_bits(args->v0.offset));
76 nvkm_wo32(chan->ramfc, 0x14, upper_32_bits(args->v0.offset));
nouveau_nvkm_engine_fifo_dmanv50.c 74 nvkm_wo32(chan->ramfc, 0x0c, upper_32_bits(args->v0.offset));
76 nvkm_wo32(chan->ramfc, 0x14, upper_32_bits(args->v0.offset));
  /src/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/engine/gr/
nouveau_nvkm_engine_gr_gm20b.c 47 hdr.code_dma_base1 = upper_32_bits((addr + adjust) >> 8);
50 hdr.data_dma_base1 = upper_32_bits((addr + adjust) >> 8);
71 .code_dma_base1 = upper_32_bits(code),
72 .data_dma_base1 = upper_32_bits(data),

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