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    Searched refs:v32i16 (Results 1 - 12 of 12) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/Target/X86/
X86TargetTransformInfo.cpp 406 { ISD::SDIV, MVT::v32i16, 6 }, // vpmulhw sequence
407 { ISD::SREM, MVT::v32i16, 8 }, // vpmulhw+mul+sub sequence
408 { ISD::UDIV, MVT::v32i16, 6 }, // vpmulhuw sequence
409 { ISD::UREM, MVT::v32i16, 8 }, // vpmulhuw+mul+sub sequence
429 { ISD::SDIV, MVT::v32i16, 12 }, // 2*vpmulhw sequence
430 { ISD::SREM, MVT::v32i16, 16 }, // 2*vpmulhw+mul+sub sequence
431 { ISD::UDIV, MVT::v32i16, 12 }, // 2*vpmulhuw sequence
432 { ISD::UREM, MVT::v32i16, 16 }, // 2*vpmulhuw+mul+sub sequence
518 { ISD::SHL, MVT::v32i16, 1 }, // vpsllvw
519 { ISD::SRL, MVT::v32i16, 1 }, // vpsrlv
1484 { ISD::SIGN_EXTEND, MVT::v32i16, MVT::v32i8, 1 }, member in class:MVT
1485 { ISD::ZERO_EXTEND, MVT::v32i16, MVT::v32i8, 1 }, member in class:MVT
1497 { ISD::SIGN_EXTEND, MVT::v32i16, MVT::v32i1, 1 }, member in class:MVT
1510 { ISD::ZERO_EXTEND, MVT::v32i16, MVT::v32i1, 2 }, member in class:MVT
1513 { ISD::TRUNCATE, MVT::v32i8, MVT::v32i16, 2 }, member in class:MVT
1524 { ISD::TRUNCATE, MVT::v32i1, MVT::v32i16, 2 }, member in class:MVT
    [all...]
X86ISelDAGToDAG.cpp 915 // Emulate v32i16/v64i8 broadcast without BWI.
916 if (!Subtarget->hasBWI() && (VT == MVT::v32i16 || VT == MVT::v64i8)) {
917 MVT NarrowVT = VT == MVT::v32i16 ? MVT::v16i16 : MVT::v32i8;
924 unsigned Index = VT == MVT::v32i16 ? 16 : 32;
939 // Emulate v32i16/v64i8 broadcast without BWI.
940 if (!Subtarget->hasBWI() && (VT == MVT::v32i16 || VT == MVT::v64i8)) {
941 MVT NarrowVT = VT == MVT::v32i16 ? MVT::v16i16 : MVT::v32i8;
952 unsigned Index = VT == MVT::v32i16 ? 16 : 32;
4333 VPTESTM_CASE(v32i16, WZ##SUFFIX)
X86ISelLowering.cpp 1519 addRegisterClass(MVT::v32i16, &X86::VR512RegClass);
1529 setLoadExtAction(ExtType, MVT::v32i16, MVT::v32i8, Legal);
1574 setTruncStoreAction(MVT::v32i16, MVT::v32i8, Legal);
1591 setOperationAction(ISD::ZERO_EXTEND, MVT::v32i16, Custom);
1594 setOperationAction(ISD::ANY_EXTEND, MVT::v32i16, Custom);
1597 setOperationAction(ISD::SIGN_EXTEND, MVT::v32i16, Custom);
1625 for (auto VT : {MVT::v32i16, MVT::v16i32, MVT::v8i64}) {
1630 setOperationAction(ISD::ADD, MVT::v32i16, HasBWI ? Legal : Custom);
1631 setOperationAction(ISD::SUB, MVT::v32i16, HasBWI ? Legal : Custom);
1637 setOperationAction(ISD::MUL, MVT::v32i16, HasBWI ? Legal : Custom)
    [all...]
X86FastISel.cpp 460 case MVT::v32i16:
631 case MVT::v32i16:
  /src/external/apache2/llvm/dist/llvm/include/llvm/Support/
MachineValueType.h 89 v32i16 = 41, // 32 x i16
412 SimpleTy == MVT::v32i16 || SimpleTy == MVT::v16i32 ||
546 case v32i16:
698 case v32i16:
950 case v32i16:
1164 if (NumElements == 32) return MVT::v32i16;
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/
ValueTypes.cpp 254 case MVT::v32i16:
  /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
HexagonISelLoweringHVX.cpp 21 static const MVT LegalV64[] = { MVT::v64i8, MVT::v32i16, MVT::v16i32 };
31 addRegisterClass(MVT::v32i16, &Hexagon::HvxVRRegClass);
236 for (MVT T: {MVT::v32i8, MVT::v32i16, MVT::v16i8, MVT::v16i16, MVT::v16i32})
239 for (MVT T: {MVT::v64i8, MVT::v64i16, MVT::v32i8, MVT::v32i16, MVT::v32i32})
HexagonISelDAGToDAG.cpp 108 case MVT::v32i16:
498 case MVT::v32i16:
HexagonInstrInfo.cpp 2689 case MVT::v32i16:
  /src/external/apache2/llvm/dist/llvm/utils/TableGen/
CodeGenTarget.cpp 108 case MVT::v32i16: return "MVT::v32i16";
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
R600ISelLowering.cpp 86 setTruncStoreAction(MVT::v32i32, MVT::v32i16, Custom);
SIISelLowering.cpp 166 setTruncStoreAction(MVT::v32i32, MVT::v32i16, Expand);
176 setTruncStoreAction(MVT::v32i16, MVT::v32i8, Expand);

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