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    Searched refs:v4i16 (Results 1 - 21 of 21) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
ARMTargetTransformInfo.cpp 459 {ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i16, 0},
460 {ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i16, 0},
496 {ISD::TRUNCATE, MVT::v4i32, MVT::v4i16, 0},
528 { ISD::ADD, MVT::v4i32, MVT::v4i16, 0 },
531 { ISD::SUB, MVT::v4i32, MVT::v4i16, 0 },
534 { ISD::MUL, MVT::v4i32, MVT::v4i16, 0 },
537 { ISD::SHL, MVT::v4i32, MVT::v4i16, 0 },
571 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i16, 1 },
572 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i16, 1 },
576 { ISD::TRUNCATE, MVT::v4i16, MVT::v4i32, 1 }
    [all...]
ARMISelLowering.cpp 407 // It is legal to extload from v4i8 to v4i16 or v4i32.
409 addAllExtLoads(MVT::v4i32, MVT::v4i16, Legal);
412 // It is legal to sign extend from v4i8/v4i16 to v4i32 or v8i8 to v8i16.
414 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i16, Legal);
420 setTruncStoreAction(MVT::v4i32, MVT::v4i16, Legal);
427 for (auto VT : {MVT::v8i8, MVT::v4i8, MVT::v4i16}) {
798 addDRTypeForNEON(MVT::v4i16);
899 setOperationAction(ISD::SDIV, MVT::v4i16, Custom);
901 setOperationAction(ISD::UDIV, MVT::v4i16, Custom);
907 setOperationAction(ISD::SINT_TO_FP, MVT::v4i16, Custom)
    [all...]
ARMISelDAGToDAG.cpp 1781 if (Alignment >= Align(2) && LoadedVT == MVT::v4i16 &&
2100 case MVT::v4i16: OpcodeIndex = 1; break;
2245 case MVT::v4i16: OpcodeIndex = 1; break;
2415 case MVT::v4i16: OpcodeIndex = 1; break;
2949 case MVT::v4i16:
4055 case MVT::v4i16: Opc = ARM::VZIPd16; break;
4078 case MVT::v4i16: Opc = ARM::VUZPd16; break;
4101 case MVT::v4i16: Opc = ARM::VTRNd16; break;
  /src/external/apache2/llvm/dist/llvm/lib/Target/X86/
X86TargetTransformInfo.cpp 1096 {TTI::SK_Broadcast, MVT::v4i16, 1}, // pshuflw
1102 {TTI::SK_Reverse, MVT::v4i16, 1}, // pshuflw
1107 {TTI::SK_PermuteTwoSrc, MVT::v4i16, 2}, // punpck/pshuflw
1113 {TTI::SK_PermuteSingleSrc, MVT::v4i16, 1}, // pshuflw
1491 { ISD::SIGN_EXTEND, MVT::v4i16, MVT::v4i1, 1 }, member in class:MVT
1504 { ISD::ZERO_EXTEND, MVT::v4i16, MVT::v4i1, 2 }, member in class:MVT
1518 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i16, 2 }, // widen to zmm member in class:MVT
1555 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i16, 3 }, // sext+vpsllq+vptestmq
1591 { ISD::SIGN_EXTEND, MVT::v4i16, MVT::v4i1, 3 },
1592 { ISD::ZERO_EXTEND, MVT::v4i16, MVT::v4i1, 4 }
1666 { ISD::SIGN_EXTEND, MVT::v4i16, MVT::v4i1, 1 }, member in class:MVT
1677 { ISD::ZERO_EXTEND, MVT::v4i16, MVT::v4i1, 2 }, member in class:MVT
1688 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i16, 2 }, \/\/ vpsllw+vptestmw member in class:MVT
    [all...]
X86ISelLowering.cpp 923 MVT::v2i16, MVT::v4i16, MVT::v2i32 }) {
1020 for (auto VT : {MVT::v2i8, MVT::v4i8, MVT::v8i8, MVT::v2i16, MVT::v4i16}) {
1053 setOperationAction(ISD::LOAD, MVT::v4i16, Custom);
1056 setOperationAction(ISD::STORE, MVT::v4i16, Custom);
1060 setOperationAction(ISD::BITCAST, MVT::v4i16, Custom);
1075 setOperationAction(ISD::TRUNCATE, MVT::v4i16, Custom);
1167 setLoadExtAction(LoadExtOp, MVT::v4i32, MVT::v4i16, Legal);
1395 setLoadExtAction(LoadExtOp, MVT::v4i64, MVT::v4i16, Legal);
1905 setTruncStoreAction(MVT::v4i64, MVT::v4i16, Legal);
1914 setTruncStoreAction(MVT::v4i32, MVT::v4i16, Legal)
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
AArch64ISelDAGToDAG.cpp 667 case MVT::v4i16:
2043 // Example: v8i16 -> v4i16 means the extract must begin at index 4.
3570 } else if (VT == MVT::v4i16 || VT == MVT::v4f16 || VT == MVT::v4bf16) {
3597 } else if (VT == MVT::v4i16 || VT == MVT::v4f16 || VT == MVT::v4bf16) {
3624 } else if (VT == MVT::v4i16 || VT == MVT::v4f16 || VT == MVT::v4bf16) {
3651 } else if (VT == MVT::v4i16 || VT == MVT::v4f16 || VT == MVT::v4bf16) {
3678 } else if (VT == MVT::v4i16 || VT == MVT::v4f16 || VT == MVT::v4bf16) {
3705 } else if (VT == MVT::v4i16 || VT == MVT::v4f16 || VT == MVT::v4bf16) {
3732 } else if (VT == MVT::v4i16 || VT == MVT::v4f16 || VT == MVT::v4bf16) {
3759 } else if (VT == MVT::v4i16 || VT == MVT::v4f16 || VT == MVT::v4bf16)
    [all...]
AArch64TargetTransformInfo.cpp 233 static const auto ValidMinMaxTys = {MVT::v8i8, MVT::v16i8, MVT::v4i16,
244 static const auto ValidSatTys = {MVT::v8i8, MVT::v16i8, MVT::v4i16,
257 static const auto ValidAbsTys = {MVT::v8i8, MVT::v16i8, MVT::v4i16,
621 { ISD::TRUNCATE, MVT::v4i16, MVT::v4i32, 1 },
644 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 3 },
645 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i16, 3 },
679 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i16, 2 },
681 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i16, 2 },
718 // Complex, from v4f32: legal type is v4i16, 1 narrowing => ~2
719 { ISD::FP_TO_SINT, MVT::v4i16, MVT::v4f32, 2 }
1629 {ISD::ADD, MVT::v4i16, 1}, member in class:MVT
    [all...]
AArch64ISelLowering.cpp 262 addDRTypeForNEON(MVT::v4i16);
1011 setOperationAction(ISD::SINT_TO_FP, MVT::v4i16, Custom);
1012 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
1018 setOperationPromotedToType(ISD::UINT_TO_FP, MVT::v4i16, MVT::v4i32);
1019 setOperationPromotedToType(ISD::SINT_TO_FP, MVT::v4i16, MVT::v4i32);
1037 for (MVT VT : { MVT::v8i8, MVT::v4i16, MVT::v2i32,
1055 for (MVT VT : { MVT::v8i8, MVT::v4i16, MVT::v2i32,
1119 setTruncStoreAction(MVT::v4i16, MVT::v4i8, Custom);
1196 MVT::v2f64, MVT::v8i8, MVT::v16i8, MVT::v4i16, MVT::v8i16,
1274 for (auto VT : {MVT::v8i8, MVT::v4i16})
    [all...]
  /src/external/apache2/llvm/dist/llvm/include/llvm/Support/
MachineValueType.h 86 v4i16 = 38, // 4 x i16
383 SimpleTy == MVT::v4i16 || SimpleTy == MVT::v2i32 ||
543 case v4i16:
749 case v4i16:
890 case v4i16:
1161 if (NumElements == 4) return MVT::v4i16;
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
SIISelLowering.cpp 126 addRegisterClass(MVT::v4i16, &AMDGPU::SReg_64RegClass);
163 setTruncStoreAction(MVT::v4i32, MVT::v4i16, Expand);
173 setTruncStoreAction(MVT::v4i16, MVT::v4i8, Expand);
218 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i16, Custom);
246 MVT::v2i64, MVT::v2f64, MVT::v4i16, MVT::v4f16,
340 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i16, Custom);
346 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i16, Custom);
359 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i16, Custom);
361 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i16, Custom);
571 for (MVT VT : {MVT::v2i16, MVT::v2f16, MVT::v4i16, MVT::v4f16})
    [all...]
AMDGPUTargetTransformInfo.cpp 804 static const auto ValidSatTys = {MVT::v2i16, MVT::v4i16};
AMDGPUISelLowering.cpp 161 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4i16, Expand);
162 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v4i16, Expand);
163 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::v4i16, Expand);
265 setTruncStoreAction(MVT::v4i64, MVT::v4i16, Expand);
1352 if (VT == MVT::v4i16 || VT == MVT::v4f16) {
R600ISelLowering.cpp 83 setTruncStoreAction(MVT::v4i32, MVT::v4i16, Custom);
171 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i16, Expand);
  /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
HexagonISelLowering.cpp 642 VT == MVT::v4i16 || VT == MVT::v8i8 ||
1478 addRegisterClass(MVT::v4i16, &Hexagon::DoubleRegsRegClass);
1683 setLoadExtAction(ISD::EXTLOAD, MVT::v4i16, MVT::v4i8, Legal);
1684 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i16, MVT::v4i8, Legal);
1685 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i16, MVT::v4i8, Legal);
1693 MVT::v8i8, MVT::v2i16, MVT::v4i16, MVT::v2i32}) {
1712 for (MVT VT : {MVT::v8i8, MVT::v4i16, MVT::v2i32}) {
1724 MVT::v2i16, MVT::v4i16, MVT::v2i32}) {
1735 for (MVT VT : {MVT::v2i16, MVT::v4i8, MVT::v8i8, MVT::v2i32, MVT::v4i16,
1752 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i16, Custom)
    [all...]
HexagonISelDAGToDAG.cpp 103 case MVT::v4i16:
493 case MVT::v4i16:
HexagonInstrInfo.cpp 2684 case MVT::v4i16:
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/
ValueTypes.cpp 248 case MVT::v4i16:
  /src/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/
WebAssemblyISelLowering.cpp 283 setLoadExtAction(Ext, MVT::v4i32, MVT::v4i16, Legal);
288 setTruncStoreAction(MVT::v4i32, MVT::v4i16, Legal);
683 (ExtT == MVT::v4i32 && MemT == MVT::v4i16) ||
2096 // Only v8i8, v4i16, and v2i32 extracts can be widened, and only if the
2104 if (Extract.getValueType() != MVT::v4i16 ||
  /src/external/apache2/llvm/dist/llvm/utils/TableGen/
CodeGenTarget.cpp 105 case MVT::v4i16: return "MVT::v4i16";
  /src/external/apache2/llvm/dist/llvm/lib/Target/NVPTX/
NVPTXISelLowering.cpp 128 case MVT::v4i16:
2293 case MVT::v4i16:
4774 case MVT::v4i16:
  /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
PPCISelLowering.cpp 848 setOperationAction(ISD::TRUNCATE, MVT::v4i16, Custom);
1059 setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::v4i16, Custom);
1063 setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::v4i16, Custom);
1067 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
1071 setOperationAction(ISD::SINT_TO_FP, MVT::v4i16, Custom);
1246 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i16, Legal);
13978 // input types (i.e. it can't handle things like v4i16) so do not run before

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