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  /src/sys/external/bsd/drm2/include/linux/
uuid.h 39 #define GUID_INIT(x, y, z, v0, v1, v2, v3, v4, v5, v6, v7) ((guid_t) \
55 [13] = (v5), \
  /src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/
zynq-zturn-v5.dts 7 model = "Zynq Z-Turn MYIR Board V5";
8 compatible = "myir,zynq-zturn-v5", "xlnx,zynq-7000";
armada-388-gp.dts 266 reg_usb2_0_vbus: v5-vbus0 {
268 regulator-name = "v5.0-vbus0";
276 reg_usb2_1_vbus: v5-vbus1 {
278 regulator-name = "v5.0-vbus1";
295 reg_5v_sata0: v5-sata0 {
297 regulator-name = "v5.0-sata0";
321 reg_5v_sata1: v5-sata1 {
323 regulator-name = "v5.0-sata1";
345 reg_5v_sata2: v5-sata2 {
347 regulator-name = "v5.0-sata2"
    [all...]
armada-385-synology-ds116.dts 204 reg_5v_sata0: v5-sata0 {
206 regulator-name = "v5.0-sata0";
  /src/sys/external/isc/libsodium/dist/src/libsodium/crypto_pwhash/argon2/
blamka-round-ref.h 27 #define BLAKE2_ROUND_NOMSG(v0, v1, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, \
31 G(v1, v5, v9, v13); \
34 G(v0, v5, v10, v15); \
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/inc/
reg_helper.h 88 f5, v5) \
94 FN(reg, f5), v5)
97 f5, v5, f6, v6) \
103 FN(reg, f5), v5,\
107 f5, v5, f6, v6, f7, v7) \
113 FN(reg, f5), v5,\
118 f5, v5, f6, v6, f7, v7, f8, v8) \
124 FN(reg, f5), v5,\
130 v5, f6, v6, f7, v7, f8, v8, f9, v9) \
136 FN(reg, f5), v5, \
    [all...]
dcn_calc_math.h 40 float dcn_bw_max5(float v1, float v2, float v3, float v4, float v5);
  /src/sys/crypto/aes/arch/arm/
aes_armv8_64.S 145 * v5.4s := (0,prk[0],prk[1],prk[2])
149 ext v5.16b, v0.16b, v1.16b, #12
155 eor v1.16b, v1.16b, v5.16b
220 * v5.4s := (0,prk[0],prk[1],prk[2])
224 ext v5.16b, v0.16b, v1.16b, #12
228 /* v5.4s := (rk[2], rk[3], nrk[0], nrk[1]) */
229 eor v5.16b, v5.16b, v1.16b
230 eor v5.16b, v5.16b, v3.16
    [all...]
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/calcs/
amdgpu_dcn_calc_math.c 106 float dcn_bw_max5(float v1, float v2, float v3, float v4, float v5)
108 return dcn_bw_max3(v1, v2, v3) > dcn_bw_max2(v4, v5) ? dcn_bw_max3(v1, v2, v3) : dcn_bw_max2(v4, v5);
  /src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/freescale/
fsl-ls1012a.dtsi 193 compatible = "fsl,sec-v5.4", "fsl,sec-v5.0",
204 compatible = "fsl,sec-v5.4-job-ring",
205 "fsl,sec-v5.0-job-ring",
212 compatible = "fsl,sec-v5.4-job-ring",
213 "fsl,sec-v5.0-job-ring",
220 compatible = "fsl,sec-v5.4-job-ring",
221 "fsl,sec-v5.0-job-ring",
228 compatible = "fsl,sec-v5.4-job-ring",
229 "fsl,sec-v5.0-job-ring"
    [all...]
fsl-ls1043a.dtsi 343 compatible = "fsl,sec-v5.4", "fsl,sec-v5.0",
354 compatible = "fsl,sec-v5.4-job-ring",
355 "fsl,sec-v5.0-job-ring",
362 compatible = "fsl,sec-v5.4-job-ring",
363 "fsl,sec-v5.0-job-ring",
370 compatible = "fsl,sec-v5.4-job-ring",
371 "fsl,sec-v5.0-job-ring",
378 compatible = "fsl,sec-v5.4-job-ring",
379 "fsl,sec-v5.0-job-ring"
    [all...]
fsl-ls1046a.dtsi 349 compatible = "fsl,sec-v5.4", "fsl,sec-v5.0",
360 compatible = "fsl,sec-v5.4-job-ring",
361 "fsl,sec-v5.0-job-ring",
368 compatible = "fsl,sec-v5.4-job-ring",
369 "fsl,sec-v5.0-job-ring",
376 compatible = "fsl,sec-v5.4-job-ring",
377 "fsl,sec-v5.0-job-ring",
384 compatible = "fsl,sec-v5.4-job-ring",
385 "fsl,sec-v5.0-job-ring"
    [all...]
imx8mq-nitrogen.dts 75 reg_vref_2v5: regulator-vref-2v5 {
77 regulator-name = "vref-2v5";
  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_atombios_crtc.c 469 PIXEL_CLOCK_PARAMETERS_V5 v5; member in union:set_pixel_clock
498 args.v5.ucCRTC = ATOM_CRTC_INVALID;
499 args.v5.usPixelClock = cpu_to_le16(dispclk);
500 args.v5.ucPpll = ATOM_DCPLL;
650 args.v5.ucCRTC = crtc_id;
651 args.v5.usPixelClock = cpu_to_le16(clock / 10);
652 args.v5.ucRefDiv = ref_div;
653 args.v5.usFbDiv = cpu_to_le16(fb_div);
654 args.v5.ulFbDivDecFrac = cpu_to_le32(frac_fb_div * 100000);
655 args.v5.ucPostDiv = post_div
    [all...]
amdgpu_atombios_encoders.c 574 DIG_ENCODER_CONTROL_PARAMETERS_V5 v5; member in union:dig_encoder_control
705 args.v5.asDPPanelModeParam.ucAction = action;
706 args.v5.asDPPanelModeParam.ucPanelMode = panel_mode;
707 args.v5.asDPPanelModeParam.ucDigId = dig->dig_encoder;
710 args.v5.asStreamParam.ucAction = action;
711 args.v5.asStreamParam.ucDigId = dig->dig_encoder;
712 args.v5.asStreamParam.ucDigMode =
714 if (ENCODER_MODE_IS_DP(args.v5.asStreamParam.ucDigMode))
715 args.v5.asStreamParam.ucLaneNum = dp_lane_count;
718 args.v5.asStreamParam.ucLaneNum = 8
762 DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_5 v5; member in union:dig_transmitter_control
    [all...]
  /src/sys/external/bsd/compiler_rt/dist/lib/tsan/rtl/
tsan_ppc_regs.h 70 #define v5 5 macro
  /src/sys/crypto/blake2/
blake2s.c 94 uint32_t v0,v1,v2,v3,v4,v5,v6,v7,v8,v9,v10,v11,v12,v13,v14,v15; local in function:blake2s_compress
104 v5 = h[5];
130 BLAKE2S_G(v1, v5, v9, v13, m[sigma[ 2]], m[sigma[ 3]]);
133 BLAKE2S_G(v0, v5, v10, v15, m[sigma[ 8]], m[sigma[ 9]]);
145 h[5] ^= v5 ^ v13;
  /src/sys/crypto/chacha/arch/arm/
chacha_neon_64.S 167 ld4r {v4.4s-v7.4s}, [x11] /* (v4,v5,v6,v7) := key[0:16) */
177 LE32TOH(v5.16b)
194 mov v21.16b, v5.16b
208 ROUND(v0,v1,v2,v3, v4,v5,v6,v7, v8,v9,v10,v11, v12,v13,v14,v15,
210 ROUND(v0,v1,v2,v3, v5,v6,v7,v4, v10,v11,v8,v9, v15,v12,v13,v14,
225 add v5.4s, v5.4s, v21.4s
242 HTOLE32(v5.16b)
255 st4 { v4.s, v5.s, v6.s, v7.s}[0], [x0], #16
259 st4 { v4.s, v5.s, v6.s, v7.s}[1], [x0], #1
    [all...]
  /src/sys/external/bsd/drm2/dist/drm/radeon/
radeon_atombios_encoders.c 1017 DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_5 v5; member in union:dig_transmitter_control
1318 args.v5.ucAction = action;
1320 args.v5.usSymClock = cpu_to_le16(dp_clock / 10);
1322 args.v5.usSymClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1327 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYB;
1329 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYA;
1333 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYD;
1335 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYC;
1339 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYF;
1341 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYE
    [all...]
radeon_atombios_crtc.c 772 PIXEL_CLOCK_PARAMETERS_V5 v5; member in union:set_pixel_clock
800 args.v5.ucCRTC = ATOM_CRTC_INVALID;
801 args.v5.usPixelClock = cpu_to_le16(dispclk);
802 args.v5.ucPpll = ATOM_DCPLL;
896 args.v5.ucCRTC = crtc_id;
897 args.v5.usPixelClock = cpu_to_le16(clock / 10);
898 args.v5.ucRefDiv = ref_div;
899 args.v5.usFbDiv = cpu_to_le16(fb_div);
900 args.v5.ulFbDivDecFrac = cpu_to_le32(frac_fb_div * 100000);
901 args.v5.ucPostDiv = post_div
    [all...]
  /src/sys/arch/powerpc/oea/
altivec_subr.S 61 li %r5,VREG_V5; lvx %v5,%r3,%r5
113 li %r5,VREG_V5; stvx %v5,%r3,%r5
  /src/sys/external/bsd/ipf/netinet/
ip_fil_compat.c 93 ipf_v5tcpinfoto4(tcpinfo_t *v5, tcpinfo4_t *v4)
95 v4->ts_sport = v5->ts_sport;
96 v4->ts_dport = v5->ts_dport;
97 v4->ts_data[0] = v5->ts_data[0];
98 v4->ts_data[1] = v5->ts_data[1];
1309 ipf_v4iptov5(frip4_t *v4, fr_ip_t *v5)
1311 v5->fi_v = v4->fi_v;
1312 v5->fi_p = v4->fi_p;
1313 v5->fi_xx = v4->fi_xx;
1314 v5->fi_tos = v4->fi_tos
    [all...]
  /src/lib/libm/src/
e_lgamma_r.c 134 v5 = 3.21709242282423911810e-03, /* 0x3F6A5ABB, 0x57D0CF61 */ variable in typeref:typename:const double
266 p2 = one+y*(v1+y*(v2+y*(v3+y*(v4+y*v5))));
e_lgammaf_r.c 70 v5 = 3.2170924824e-03, /* 0x3b52d5db */ variable in typeref:typename:const float
202 p2 = one+y*(v1+y*(v2+y*(v3+y*(v4+y*v5))));
  /src/lib/libm/ld128/
e_lgammal_r.c 122 v5 = 5.14448694179047879915042998453632434e+00L, variable in typeref:typename:const long double
291 p2 = one+y*(v1+y*(v2+y*(v3+y*(v4+y*(v5+y*(v6+y*(v7+

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