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    Searched refs:v8i1 (Results 1 - 12 of 12) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/Target/X86/
X86TargetTransformInfo.cpp 1492 { ISD::SIGN_EXTEND, MVT::v8i8, MVT::v8i1, 1 }, member in class:MVT
1493 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i1, 1 }, member in class:MVT
1505 { ISD::ZERO_EXTEND, MVT::v8i8, MVT::v8i1, 2 }, member in class:MVT
1506 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v8i1, 2 }, member in class:MVT
1519 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i8, 2 }, // widen to zmm member in class:MVT
1520 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i16, 2 }, // widen to zmm member in class:MVT
1552 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i8, 3 }, // sext+vpslld+vptestmd
1556 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i16, 3 }, // sext+vpsllq+vptestmq
1560 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i32, 2 }, // zmm vpslld+vptestmd
1564 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i64, 2 }, // vpsllq+vptestm
1667 { ISD::SIGN_EXTEND, MVT::v8i8, MVT::v8i1, 1 }, member in class:MVT
1668 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i1, 1 }, member in class:MVT
1678 { ISD::ZERO_EXTEND, MVT::v8i8, MVT::v8i1, 2 }, member in class:MVT
1679 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v8i1, 2 }, member in class:MVT
1689 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i8, 2 }, \/\/ vpsllw+vptestmb member in class:MVT
1690 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i16, 2 }, \/\/ vpsllw+vptestmw member in class:MVT
    [all...]
X86ISelLowering.cpp 1447 addRegisterClass(MVT::v8i1, &X86::VK8RegClass);
1454 setOperationPromotedToType(ISD::FP_TO_SINT, MVT::v8i1, MVT::v8i32);
1455 setOperationPromotedToType(ISD::FP_TO_UINT, MVT::v8i1, MVT::v8i32);
1458 setOperationPromotedToType(ISD::STRICT_FP_TO_SINT, MVT::v8i1, MVT::v8i32);
1459 setOperationPromotedToType(ISD::STRICT_FP_TO_UINT, MVT::v8i1, MVT::v8i32);
1472 setOperationAction(ISD::LOAD, MVT::v8i1, Custom);
1477 setOperationAction(ISD::STORE, MVT::v8i1, Custom);
1480 // Extends of v16i1/v8i1/v4i1/v2i1 to 128-bit vectors.
1487 for (auto VT : { MVT::v1i1, MVT::v2i1, MVT::v4i1, MVT::v8i1, MVT::v16i1 })
1490 for (auto VT : { MVT::v2i1, MVT::v4i1, MVT::v8i1, MVT::v16i1 })
    [all...]
  /src/external/apache2/llvm/dist/llvm/include/llvm/Support/
MachineValueType.h 64 v8i1 = 18, // 8 x i1
509 case v8i1:
727 case v8i1:
851 case v8i1: return TypeSize::Fixed(8);
1137 if (NumElements == 8) return MVT::v8i1;
  /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
HexagonISelLowering.cpp 1472 addRegisterClass(MVT::v8i1, &Hexagon::PredRegsRegClass); // hgfedcba
1692 for (MVT NativeVT : {MVT::v8i1, MVT::v4i1, MVT::v2i1, MVT::v4i8,
1730 for (MVT VT : {MVT::v2i1, MVT::v4i1, MVT::v8i1}) {
1746 // Custom-lower bitcasts from i8 to v8i1.
2315 // Handle conversion from i8 to v8i1.
2317 if (ResTy == MVT::v8i1) {
2535 // Each bool vector (v2i1, v4i1, v8i1) always occupies 8 bits in
2737 if (VecTy == MVT::v8i1 || VecTy == MVT::v4i1 || VecTy == MVT::v2i1) {
2790 assert(VecTy == MVT::v2i1 || VecTy == MVT::v4i1 || VecTy == MVT::v8i1);
2889 // Lower loads of scalar predicate vectors (v2i1, v4i1, v8i1) to loads of i
    [all...]
HexagonISelDAGToDAG.cpp 808 SDNode *Pu = CurDAG->getMachineNode(Hexagon::C2_tfrrp, dl, MVT::v8i1,
HexagonISelLoweringHVX.cpp 682 assert(PredTy == MVT::v2i1 || PredTy == MVT::v4i1 || PredTy == MVT::v8i1);
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/
ValueTypes.cpp 208 case MVT::v8i1:
  /src/external/apache2/llvm/dist/llvm/utils/TableGen/
CodeGenTarget.cpp 85 case MVT::v8i1: return "MVT::v8i1";
  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
AArch64TargetTransformInfo.cpp 1136 { ISD::SELECT, MVT::v8i1, MVT::v8i32, 8 },
1139 { ISD::SELECT, MVT::v8i1, MVT::v8i64, 8 * AmortizationCost },
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
ARMTargetTransformInfo.cpp 918 { ISD::SELECT, MVT::v8i1, MVT::v8i64, 50 },
ARMISelLowering.cpp 436 const MVT pTypes[] = {MVT::v16i1, MVT::v8i1, MVT::v4i1};
8108 case MVT::v8i1:
8134 // If the real predicate is an v8i1 or v4i1 (not v16i1) then we need to recast
8187 // which will generate a real predicate, i.e. v4i1, v8i1 or v16i1.
8658 // We now have Op1 + Op2 promoted to vectors of integers, where v8i1 gets
8665 // the promoted vector is v4i32. The result of concatentation gives a v8i1,
8686 // which will generate a real predicate, i.e. v4i1, v8i1 or v16i1.
8733 // We now have Op1 promoted to a vector of integers, where v8i1 gets
8748 // which will generate a real predicate, i.e. v4i1, v8i1 or v16i1.
8758 assert((VT == MVT::v16i1 || VT == MVT::v8i1 || VT == MVT::v4i1) &
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/
RISCVISelLowering.cpp 1368 // XLenVT if we're producing a v8i1. This results in more consistent
1420 Vec = DAG.getBitcast(MVT::v8i1, Vec);
3830 // elements to safely divide by 8: v8i1 = extract nxv1i1 is valid.
4077 VT = MVT::v8i1;

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