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    Searched refs:v8i8 (Results 1 - 19 of 19) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
ARMTargetTransformInfo.cpp 463 {ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i8, 0},
464 {ISD::ZERO_EXTEND, MVT::v8i16, MVT::v8i8, 0},
498 {ISD::TRUNCATE, MVT::v8i16, MVT::v8i8, 0},
500 {ISD::TRUNCATE, MVT::v8i32, MVT::v8i8, 1},
529 { ISD::ADD, MVT::v8i16, MVT::v8i8, 0 },
532 { ISD::SUB, MVT::v8i16, MVT::v8i8, 0 },
535 { ISD::MUL, MVT::v8i16, MVT::v8i8, 0 },
538 { ISD::SHL, MVT::v8i16, MVT::v8i8, 0 },
579 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i8, 1 },
580 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v8i8, 1 }
    [all...]
ARMISelLowering.cpp 408 addAllExtLoads(MVT::v8i16, MVT::v8i8, Legal);
412 // It is legal to sign extend from v4i8/v4i16 to v4i32 or v8i8 to v8i16.
416 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v8i8, Legal);
422 setTruncStoreAction(MVT::v8i16, MVT::v8i8, Legal);
427 for (auto VT : {MVT::v8i8, MVT::v4i8, MVT::v4i16}) {
797 addDRTypeForNEON(MVT::v8i8);
900 setOperationAction(ISD::SDIV, MVT::v8i8, Custom);
902 setOperationAction(ISD::UDIV, MVT::v8i8, Custom);
921 // v8i8/v16i8 vcnt instruction.
933 setOperationAction(ISD::CTTZ, MVT::v8i8, Custom)
    [all...]
ARMISelDAGToDAG.cpp 1787 } else if (LoadedVT == MVT::v8i8 &&
2097 case MVT::v8i8: OpcodeIndex = 0; break;
2242 case MVT::v8i8: OpcodeIndex = 0; break;
2412 case MVT::v8i8: OpcodeIndex = 0; break;
2947 case MVT::v8i8:
4053 case MVT::v8i8: Opc = ARM::VZIPd8; break;
4076 case MVT::v8i8: Opc = ARM::VUZPd8; break;
4099 case MVT::v8i8: Opc = ARM::VTRNd8; break;
  /src/external/apache2/llvm/dist/llvm/lib/Target/X86/
X86TargetTransformInfo.cpp 1098 {TTI::SK_Broadcast, MVT::v8i8, 2}, // punpck/pshuflw
1109 {TTI::SK_PermuteTwoSrc, MVT::v8i8, 7}, // punpck/pshuflw
1115 {TTI::SK_PermuteSingleSrc, MVT::v8i8, 5}, // punpck/pshuflw
1492 { ISD::SIGN_EXTEND, MVT::v8i8, MVT::v8i1, 1 }, member in class:MVT
1505 { ISD::ZERO_EXTEND, MVT::v8i8, MVT::v8i1, 2 }, member in class:MVT
1519 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i8, 2 }, // widen to zmm member in class:MVT
1552 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i8, 3 }, // sext+vpslld+vptestmd
1567 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i64, 2 },
1582 { ISD::SIGN_EXTEND, MVT::v8i8, MVT::v8i1, 3 },
1583 { ISD::ZERO_EXTEND, MVT::v8i8, MVT::v8i1, 4 }
1667 { ISD::SIGN_EXTEND, MVT::v8i8, MVT::v8i1, 1 }, member in class:MVT
1678 { ISD::ZERO_EXTEND, MVT::v8i8, MVT::v8i1, 2 }, member in class:MVT
1689 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i8, 2 }, \/\/ vpsllw+vptestmb member in class:MVT
    [all...]
X86ISelLowering.cpp 922 for (auto VT : { MVT::v2i8, MVT::v4i8, MVT::v8i8,
932 setOperationAction(ISD::MUL, MVT::v8i8, Custom);
1020 for (auto VT : {MVT::v2i8, MVT::v4i8, MVT::v8i8, MVT::v2i16, MVT::v4i16}) {
1054 setOperationAction(ISD::LOAD, MVT::v8i8, Custom);
1057 setOperationAction(ISD::STORE, MVT::v8i8, Custom);
1061 setOperationAction(ISD::BITCAST, MVT::v8i8, Custom);
1076 setOperationAction(ISD::TRUNCATE, MVT::v8i8, Custom);
1164 setLoadExtAction(LoadExtOp, MVT::v8i16, MVT::v8i8, Legal);
1392 setLoadExtAction(LoadExtOp, MVT::v8i32, MVT::v8i8, Legal);
1525 setLoadExtAction(ExtType, MVT::v8i64, MVT::v8i8, Legal)
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
AArch64ISelDAGToDAG.cpp 3564 if (VT == MVT::v8i8) {
3591 if (VT == MVT::v8i8) {
3618 if (VT == MVT::v8i8) {
3645 if (VT == MVT::v8i8) {
3672 if (VT == MVT::v8i8) {
3699 if (VT == MVT::v8i8) {
3726 if (VT == MVT::v8i8) {
3753 if (VT == MVT::v8i8) {
3780 if (VT == MVT::v8i8) {
3807 if (VT == MVT::v16i8 || VT == MVT::v8i8) {
    [all...]
AArch64TargetTransformInfo.cpp 233 static const auto ValidMinMaxTys = {MVT::v8i8, MVT::v16i8, MVT::v4i16,
244 static const auto ValidSatTys = {MVT::v8i8, MVT::v16i8, MVT::v4i16,
257 static const auto ValidAbsTys = {MVT::v8i8, MVT::v16i8, MVT::v4i16,
623 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i32, 3 },
648 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i8, 3 },
649 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i8, 3 },
652 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i8, 7 },
653 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i8, 7 },
684 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i8, 10 },
686 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i8, 10 }
1627 {ISD::ADD, MVT::v8i8, 1}, member in class:MVT
    [all...]
AArch64ISelLowering.cpp 261 addDRTypeForNEON(MVT::v8i8);
995 setOperationPromotedToType(ISD::SINT_TO_FP, MVT::v8i8, MVT::v8i32);
996 setOperationPromotedToType(ISD::UINT_TO_FP, MVT::v8i8, MVT::v8i32);
1026 setOperationAction(ISD::BITREVERSE, MVT::v8i8, Legal);
1037 for (MVT VT : { MVT::v8i8, MVT::v4i16, MVT::v2i32,
1055 for (MVT VT : { MVT::v8i8, MVT::v4i16, MVT::v2i32,
1196 MVT::v2f64, MVT::v8i8, MVT::v16i8, MVT::v4i16, MVT::v8i16,
1274 for (auto VT : {MVT::v8i8, MVT::v4i16})
1295 setOperationAction(ISD::SDIV, MVT::v8i8, Custom);
1307 setOperationAction(ISD::UDIV, MVT::v8i8, Custom)
    [all...]
  /src/external/apache2/llvm/dist/llvm/include/llvm/Support/
MachineValueType.h 76 v8i8 = 29, // 8 x i8
382 return (SimpleTy == MVT::v64i1 || SimpleTy == MVT::v8i8 ||
527 case v8i8:
728 case v8i8:
889 case v8i8:
1150 if (NumElements == 8) return MVT::v8i8;
  /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
HexagonISelLowering.cpp 642 VT == MVT::v4i16 || VT == MVT::v8i8 ||
1477 addRegisterClass(MVT::v8i8, &Hexagon::DoubleRegsRegClass);
1693 MVT::v8i8, MVT::v2i16, MVT::v4i16, MVT::v2i32}) {
1712 for (MVT VT : {MVT::v8i8, MVT::v4i16, MVT::v2i32}) {
1723 for (MVT VT : {MVT::i16, MVT::i32, MVT::v4i8, MVT::i64, MVT::v8i8,
1735 for (MVT VT : {MVT::v2i16, MVT::v4i8, MVT::v8i8, MVT::v2i32, MVT::v4i16,
1753 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i8, Custom);
1780 MVT::v2i16, MVT::v2i32, MVT::v4i8, MVT::v4i16, MVT::v8i8}) {
HexagonISelDAGToDAG.cpp 104 case MVT::v8i8:
494 case MVT::v8i8:
HexagonISelLoweringHVX.cpp 1008 // Combine the two low words from ShuffV into a v8i8, and byte-compare
1013 SDValue Vec64 = DAG.getNode(HexagonISD::COMBINE, dl, MVT::v8i8, {W1, W0});
HexagonInstrInfo.cpp 2685 case MVT::v8i8:
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/
ValueTypes.cpp 230 case MVT::v8i8:
  /src/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/
WebAssemblyISelLowering.cpp 282 setLoadExtAction(Ext, MVT::v8i16, MVT::v8i8, Legal);
287 setTruncStoreAction(MVT::v8i16, MVT::v8i8, Legal);
682 return (ExtT == MVT::v8i16 && MemT == MVT::v8i8) ||
2096 // Only v8i8, v4i16, and v2i32 extracts can be widened, and only if the
2100 if (Extract.getValueType() != MVT::v8i8 ||
  /src/external/apache2/llvm/dist/llvm/utils/TableGen/
CodeGenTarget.cpp 96 case MVT::v8i8: return "MVT::v8i8";
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
SIISelLowering.cpp 169 setTruncStoreAction(MVT::v8i32, MVT::v8i8, Expand);
174 setTruncStoreAction(MVT::v8i16, MVT::v8i8, Expand);
179 setTruncStoreAction(MVT::v8i64, MVT::v8i8, Expand);
353 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i8, Custom);
357 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i8, Custom);
759 for (MVT VT : { MVT::v4i16, MVT::v4f16, MVT::v2i8, MVT::v4i8, MVT::v8i8 }) {
R600ISelLowering.cpp 89 setTruncStoreAction(MVT::v8i32, MVT::v8i8, Custom);
  /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
PPCISelLowering.cpp 845 setOperationAction(ISD::TRUNCATE, MVT::v8i8, Custom);

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