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    Searched refs:v_addressable (Results 1 - 25 of 27) sorted by relevancy

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  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn10/
amdgpu_dcn10_opp.c 320 uint32_t space1_size = timing->v_total - timing->v_addressable;
322 uint32_t space2_size = timing->v_total - timing->v_addressable;
amdgpu_dcn10_optc.c 233 patched_crtc_timing.v_addressable -
320 patched_crtc_timing.v_addressable -
525 v_blank = (timing->v_total - timing->v_addressable -
1264 hw_crtc_timing->v_addressable = s.v_total - ((s.v_total - s.v_blank_start) + s.v_blank_end);
amdgpu_dcn10_stream_encoder.c 278 hw_crtc_timing.v_addressable /= 2;
452 hw_crtc_timing.v_addressable - hw_crtc_timing.v_border_bottom -
476 hw_crtc_timing.v_addressable + hw_crtc_timing.v_border_bottom);
  /src/sys/external/bsd/drm2/dist/drm/amd/display/include/
bios_parser_types.h 174 uint32_t v_addressable; member in struct:bp_hw_crtc_timing_parameters
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/bios/
amdgpu_command_table2.c 504 params.v_size = cpu_to_le16((uint16_t)bp_params->v_addressable);
508 bp_params->v_addressable));
523 bp_params->v_addressable));
amdgpu_command_table.c 1762 params.usV_Disp = cpu_to_le16((uint16_t)(bp_params->v_addressable));
1836 params.usV_Size = cpu_to_le16((uint16_t)bp_params->v_addressable);
1839 cpu_to_le16((uint16_t)(bp_params->v_total - bp_params->v_addressable));
1850 cpu_to_le16((uint16_t)(bp_params->v_sync_start - bp_params->v_addressable));
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce110/
amdgpu_dce110_timing_generator_v.c 253 uint32_t v_sync_start = timing->v_addressable + vsync_offset;
316 tmp = tmp + timing->v_addressable + timing->v_border_top +
amdgpu_dce110_timing_generator.c 297 uint32_t v_sync_start =dc_crtc_timing->v_addressable + vsync_offset;
319 bp_params.v_addressable = patched_crtc_timing.v_addressable;
612 uint32_t v_sync_start =timing->v_addressable + vsync_offset;
697 tmp = tmp + timing->v_addressable + timing->v_border_top +
amdgpu_dce110_hw_sequencer.c 1137 stream->timing.v_addressable
1859 params.source_view_height = pipe_ctx->stream->timing.v_addressable;
amdgpu_dce110_resource.c 965 context->streams[0]->timing.v_addressable,
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/clk_mgr/dce110/
amdgpu_dce110_clk_mgr.c 113 - stream->timing.v_addressable);
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce120/
amdgpu_dce120_timing_generator.c 113 (timing->v_total - timing->v_addressable -
441 uint32_t v_sync_start = timing->v_addressable + vsync_offset;
482 tmp2 = tmp1 + timing->v_addressable + timing->v_border_top +
676 timing->v_total - timing->v_addressable -
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/core/
amdgpu_dc_link_hwss.c 434 dsc_cfg.pic_height = stream->timing.v_addressable + stream->timing.v_border_top + stream->timing.v_border_bottom;
538 dsc_cfg.pic_height = stream->timing.v_addressable + stream->timing.v_border_top + stream->timing.v_border_bottom;
amdgpu_dc.c 365 param.windowa_y_end = pipe->stream->timing.v_addressable;
369 param.windowb_y_end = pipe->stream->timing.v_addressable;
1121 if (crtc_timing->v_addressable != hw_crtc_timing.v_addressable)
1277 context->streams[i]->timing.v_addressable,
amdgpu_dc_resource.c 381 if (stream1->timing.v_addressable
382 != stream2->timing.v_addressable)
1027 pipe_ctx->plane_res.scl_data.v_active = timing->v_addressable +
amdgpu_dc_link_dp.c 2226 timing->v_addressable == (uint32_t) 480)
3638 int height = pipe_ctx->stream->timing.v_addressable +
amdgpu_dc_link.c 2080 && (stream->timing.v_addressable == 480);
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/
dc_hw_types.h 724 uint32_t v_addressable; member in struct:dc_crtc_timing
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce/
amdgpu_dce_stream_encoder.c 305 hw_crtc_timing.v_addressable /= 2;
494 hw_crtc_timing.v_addressable - hw_crtc_timing.v_border_bottom -
522 hw_crtc_timing.v_addressable + hw_crtc_timing.v_border_bottom);
dce_clk_mgr.c 561 - stream->timing.v_addressable);
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/calcs/
amdgpu_dcn_calcs.c 413 input->dest.vactive = pipe->stream->timing.v_addressable + pipe->stream->timing.v_border_top
432 - pipe->stream->timing.v_addressable
881 v->vactive[input_idx] = pipe->stream->timing.v_addressable +
895 v->viewport_height[input_idx] = pipe->stream->timing.v_addressable;
1190 vesa_sync_start = pipe->stream->timing.v_addressable +
1201 pipe->stream->timing.v_addressable +
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dsc/
amdgpu_dc_dsc.c 586 pic_height = timing->v_addressable + timing->v_border_top + timing->v_border_bottom;
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn20/
amdgpu_dcn20_resource.c 1933 (v_total - timing->v_addressable
1949 - timing->v_addressable
1955 pipes[pipe_cnt].pipe.dest.vactive = timing->v_addressable;
2076 pipes[pipe_cnt].pipe.src.viewport_height = timing->v_addressable;
2306 dsc_cfg.pic_height = stream->timing.v_addressable + stream->timing.v_border_top
amdgpu_dcn20_hwseq.c 950 int height = stream->timing.v_addressable + stream->timing.v_border_bottom + stream->timing.v_border_top;
  /src/sys/external/bsd/drm2/dist/drm/amd/display/amdgpu_dm/
amdgpu_dm.c 3573 dst.height = stream->timing.v_addressable;
3593 dst.y = (stream->timing.v_addressable - dst.height) / 2;
3829 timing_out->v_addressable = mode_in->crtc_vdisplay;

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