| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce/ |
| amdgpu_dce_transform.c | 127 if (data->taps.h_taps + data->taps.v_taps <= 2) {
138 SCL_V_NUM_OF_TAPS, data->taps.v_taps - 1);
281 dc_fixpt_from_int(data->taps.v_taps + 1)),
357 coeffs_v = get_filter_coeffs_16p(data->taps.v_taps, data->ratios.vert);
367 data->taps.v_taps,
372 data->taps.v_taps,
915 if (in_taps->v_taps >= max_num_of_lines)
928 scl_data->taps.v_taps = decide_taps(scl_data->ratios.vert, in_taps->v_taps, false);
930 scl_data->taps.v_taps_c = decide_taps(scl_data->ratios.vert_c, in_taps->v_taps, true)
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn20/ |
| amdgpu_dcn20_dpp.c | 416 if (in_taps->v_taps == 0) {
418 scl_data->taps.v_taps = 8;
420 scl_data->taps.v_taps = 4;
422 scl_data->taps.v_taps = in_taps->v_taps;
445 scl_data->taps.v_taps = 1;
|
| amdgpu_dcn20_dwb_scl.c | 809 uint32_t v_taps_luma = num_taps.v_taps;
|
| amdgpu_dcn20_resource.c | 2159 pipes[pipe_cnt].pipe.scale_taps.vtaps = scl->taps.v_taps;
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn10/ |
| amdgpu_dcn10_dpp.c | 178 if (in_taps->v_taps == 0)
179 scl_data->taps.v_taps = 4;
181 scl_data->taps.v_taps = in_taps->v_taps;
198 scl_data->taps.v_taps = 1;
|
| amdgpu_dcn10_dpp_dscl.c | 321 v_2tap_hardcode_coef_en = scl_data->taps.v_taps < 3
323 && (scl_data->taps.v_taps > 1 && scl_data->taps.v_taps_c > 1);
342 scl_data->taps.v_taps, scl_data->ratios.vert);
367 dpp, scl_data->taps.v_taps,
486 int vtaps = scl_data->taps.v_taps;
573 SCL_V_NUM_TAPS, scl_data->taps.v_taps - 1,
733 SCL_V_NUM_TAPS, scl_data->taps.v_taps - 1,
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce110/ |
| amdgpu_dce110_transform_v.c | 174 set_reg_field_value(value, data->taps.v_taps - 1,
183 if (data->taps.h_taps + data->taps.v_taps > 2) {
567 coeffs_v = get_filter_coeffs_64p(data->taps.v_taps, data->ratios.vert);
579 data->taps.v_taps,
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/core/ |
| amdgpu_dc_debug.c | 82 "plane_state->scaling_quality.v_taps = %d;\n"
91 plane_state->scaling_quality.v_taps,
279 "scaling_info->scaling_quality.v_taps = %d;\n"
295 update->scaling_info->scaling_quality.v_taps,
|
| amdgpu_dc_resource.c | 896 dc_fixpt_add_int(data->ratios.vert, data->taps.v_taps + 1), 2), 19);
909 orthogonal_rotation ? data->taps.v_taps : data->taps.h_taps,
927 orthogonal_rotation ? data->taps.h_taps : data->taps.v_taps,
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/ |
| dc_hw_types.h | 580 uint32_t v_taps; member in struct:scaling_taps
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/calcs/ |
| amdgpu_dce_calcs.c | 374 data->v_taps[maximum_number_of_surfaces - 2] = bw_int_to_fixed(1);
375 data->v_taps[maximum_number_of_surfaces - 1] = bw_int_to_fixed(1);
427 data->v_taps[i] = bw_int_to_fixed(1);
536 if (bw_mtn(data->vsr[i], data->v_taps[i])) {
572 if (bw_mtn(bw_add(data->v_taps[i], bw_int_to_fixed(1)), data->lb_partitions[i])) {
795 data->v_filter_init[i] = bw_floor2(bw_div((bw_add(bw_add(bw_add(bw_int_to_fixed(1), data->v_taps[i]), data->vsr[i]), bw_mul(bw_mul(bw_int_to_fixed(data->interlace_mode[i]), bw_frc_to_fixed(5, 10)), data->vsr[i]))), bw_int_to_fixed(2)), bw_int_to_fixed(1));
815 else if ((((dceip->underlay_downscale_prefetch_enabled == 1 && surface_type[i] != bw_def_graphics) || surface_type[i] == bw_def_graphics) && (bw_mtn(data->lb_partitions[i], bw_add(data->v_taps[i], bw_ceil2(data->vsr[i], bw_int_to_fixed(1))))))) {
1249 data->scaler_limits_factor = bw_max2(bw_div(data->v_taps[i], data->v_scaler_efficiency), bw_div(data->source_width_rounded_up_to_chunks[i], data->h_total[i]));
1252 data->scaler_limits_factor = bw_max3(bw_int_to_fixed(1), bw_ceil2(bw_div(data->h_taps[i], bw_int_to_fixed(4)), bw_int_to_fixed(1)), bw_mul(data->hsr[i], bw_max2(bw_div(data->v_taps[i], data->v_scaler_efficiency), bw_int_to_fixed(1))));
1307 if (dceip->graphics_lb_nodownscaling_multi_line_prefetching == 1 && (bw_equ(data->vsr[i], bw_int_to_fixed(1)) || (bw_leq(data->vsr[i], bw_frc_to_fixed(8, 10)) && bw_leq(data->v_taps[i], bw_int_to_fixed(2)) && data->lb_bpc[i] == 8)) && surface_type[i] == bw_def_graphics)
[all...] |
| calcs_logger.h | 433 DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] v_taps[%d]:%d", i, bw_fixed_to_int(data->v_taps[i]));
|
| amdgpu_dcn_calcs.c | 395 input->scale_taps.vtaps = pipe->plane_res.scl_data.taps.v_taps;
987 v->override_vta_ps[input_idx] = pipe->plane_res.scl_data.taps.v_taps;
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/inc/ |
| dce_calcs.h | 399 struct bw_fixed v_taps[maximum_number_of_surfaces]; member in struct:bw_calcs_data
|
