| /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/ |
| amdgpu_vce.c | 97 * amdgpu_vce_init - allocate memory, load vce firmware
101 * First step to get VCE online, allocate memory and load the firmware
166 r = request_firmware(&adev->vce.fw, fw_name, adev->dev);
173 r = amdgpu_ucode_validate(adev->vce.fw);
177 release_firmware(adev->vce.fw);
178 adev->vce.fw = NULL;
182 hdr = (const struct common_firmware_header *)adev->vce.fw->data;
188 DRM_INFO("Found VCE firmware Version: %x.%x Binary ID: %x\n",
190 adev->vce.fw_version = ((version_major << 24) | (version_minor << 16) |
194 AMDGPU_GEM_DOMAIN_VRAM, &adev->vce.vcpu_bo
[all...] |
| amdgpu_vce_v4_0.c | 41 #include "vce/vce_4_0_offset.h"
42 #include "vce/vce_4_0_default.h"
43 #include "vce/vce_4_0_sh_mask.h"
47 #include "ivsrcid/vce/irqsrcs_vce_4_0.h"
73 return RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_RPTR));
75 return RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_RPTR2));
77 return RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_RPTR3));
95 return RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_WPTR));
97 return RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_WPTR2));
99 return RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_WPTR3))
[all...] |
| amdgpu_vce_v3_0.c | 38 #include "vce/vce_3_0_d.h"
39 #include "vce/vce_3_0_sh_mask.h"
88 if (adev->vce.harvest_config == 0 ||
89 adev->vce.harvest_config == AMDGPU_VCE_HARVEST_VCE1)
91 else if (adev->vce.harvest_config == AMDGPU_VCE_HARVEST_VCE0)
120 if (adev->vce.harvest_config == 0 ||
121 adev->vce.harvest_config == AMDGPU_VCE_HARVEST_VCE1)
123 else if (adev->vce.harvest_config == AMDGPU_VCE_HARVEST_VCE0)
151 if (adev->vce.harvest_config == 0 ||
152 adev->vce.harvest_config == AMDGPU_VCE_HARVEST_VCE1
[all...] |
| amdgpu_vce_v2_0.c | 38 #include "vce/vce_2_0_d.h"
39 #include "vce/vce_2_0_sh_mask.h"
134 DRM_ERROR("VCE not responding, trying to reset the ECPU!!!\n");
188 WREG32(mmVCE_LMI_VCPU_CACHE_40BIT_BAR, (adev->vce.gpu_addr >> 8));
229 * vce_v2_0_start - start VCE block
233 * Setup and start the VCE block
248 ring = &adev->vce.ring[0];
255 ring = &adev->vce.ring[1];
273 DRM_ERROR("VCE not responding, giving up!!!\n");
286 DRM_INFO("vce is not idle \n")
[all...] |
| amdgpu_kms.c | 222 fw_info->ver = adev->vce.fw_version;
223 fw_info->feature = adev->vce.fb_version;
370 for (i = 0; i < adev->vce.num_rings; i++)
371 if (adev->vce.ring[i].sched.ready)
730 /* Older VCE FW versions are buggy and can handle only 40bits */
731 if (adev->vce.fw_version &&
732 adev->vce.fw_version < AMDGPU_VCE_FW_53_45)
755 dev_info.vce_harvest_config = adev->vce.harvest_config;
1254 /* VCE */
1259 seq_printf(m, "VCE feature version: %u, firmware version: 0x%08x\n"
[all...] |
| amdgpu_ctx.c | 107 sched = &adev->vce.ring[0].sched;
|
| amdgpu_ucode.c | 401 FW_VERSION_ATTR(vce_fw_version, 0444, vce.fw_version);
612 * if SMU loaded firmware, it needn't add SMC, UVD, and VCE
|
| amdgpu.h | 909 /* vce */
910 struct amdgpu_vce vce; member in struct:amdgpu_device
|
| /src/sys/external/bsd/drm2/dist/drm/radeon/ |
| radeon_vce.c | 93 * radeon_vce_init - allocate memory, load vce firmware
97 * First step to get VCE online, allocate memory and load the firmware
108 INIT_DELAYED_WORK(&rdev->vce.idle_work, radeon_vce_idle_work_handler);
175 if (!scan_2dec_uint(&c, ']', &rdev->vce.fb_version))
178 if (sscanf(c, "%2u]", &rdev->vce.fb_version) != 1)
182 DRM_INFO("Found VCE firmware/feedback version %hhd.%hhd.%hhd / %d!\n",
183 start, mid, end, rdev->vce.fb_version);
185 rdev->vce.fw_version = (start << 24) | (mid << 16) | (end << 8);
188 if ((rdev->vce.fw_version != ((40 << 24) | (2 << 16) | (2 << 8))) &&
189 (rdev->vce.fw_version != ((50 << 24) | (0 << 16) | (1 << 8))) &
[all...] |
| radeon_vce_v1_0.c | 210 rdev->vce.keyselect = le32_to_cpu(sign->val[i].keyselect);
223 uint64_t addr = rdev->vce.gpu_addr;
259 WREG32(VCE_LMI_FW_START_KEYSEL, rdev->vce.keyselect);
288 * vce_v1_0_start - start VCE block
292 * Setup and start the VCE block
342 DRM_ERROR("VCE not responding, trying to reset the ECPU!!!\n");
354 DRM_ERROR("VCE not responding, giving up!!!\n");
386 DRM_INFO("VCE initialized successfully.\n");
|
| radeon_vce_v2_0.c | 164 uint64_t addr = rdev->vce.gpu_addr;
|
| radeon_drv.c | 105 * 2.42.0 - Add VCE/VUI (Video Usability Information) support
315 MODULE_PARM_DESC(vce, "vce enable/disable vce support (1 = enable, 0 = disable)");
316 module_param_named(vce, radeon_vce, int, 0444);
|
| radeon_kms.c | 530 *value = rdev->vce.fw_version;
533 *value = rdev->vce.fb_version;
|
| /src/sys/dev/hyperv/ |
| vmbus.c | 2199 struct vmbus_chev *vce; local
2201 vce = kmem_intr_alloc(sizeof(*vce), KM_NOSLEEP);
2202 if (vce == NULL) {
2207 vce->vce_type = type;
2208 vce->vce_arg = arg;
2211 SIMPLEQ_INSERT_TAIL(&sc->sc_chevq, vce, vce_entry);
2220 struct vmbus_chev *vce; local
2227 vce = SIMPLEQ_FIRST(&sc->sc_chevq);
2231 switch (vce->vce_type)
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/hwmgr/ |
| smu10_hwmgr.h | 113 uint32_t vce : 1; member in struct:pp_disable_nbpslo_flags::__anon4715::__anon4716
|
| smu8_hwmgr.h | 136 uint32_t vce : 1; member in struct:pp_disable_nb_ps_flags::__anon4717::__anon4718
|
| /src/external/gpl3/gcc/dist/gcc/ |
| ipa-param-manipulation.cc | 1972 tree vce = build1 (VIEW_CONVERT_EXPR, TREE_TYPE (expr), repl); local
1977 vce = force_gimple_operand (vce, extra_stmts, true, NULL_TREE);
1979 *expr_p = vce;
|
| omp-simd-clone.cc | 1117 tree vce = build1 (VIEW_CONVERT_EXPR, TREE_TYPE (*tp), repl); local
1118 *tp = vce;
|
| ipa-prop.cc | 5642 bool by_ref, vce; local
5650 vce = false;
5658 vce = true;
5663 if (vce)
|
| tree-sra.cc | 4382 bool vce = false; local
4387 vce = true;
4390 if (lacc->grp_partial_lhs && (vce || racc->grp_partial_lhs))
|
| tree-ssa-reassoc.cc | 2116 tree vce = build1 (VIEW_CONVERT_EXPR, vec_type, sum_vec); local
2118 gimple *g = gimple_build_assign (lhs, VIEW_CONVERT_EXPR, vce);
2128 tree vce = build1 (VIEW_CONVERT_EXPR, vec_type, local
2131 gimple *g = gimple_build_assign (lhs, VIEW_CONVERT_EXPR, vce);
|
| /src/external/gpl3/gcc.old/dist/gcc/ |
| ipa-param-manipulation.cc | 1811 tree vce = build1 (VIEW_CONVERT_EXPR, TREE_TYPE (expr), repl); local
1812 *expr_p = vce;
|
| omp-simd-clone.cc | 950 tree vce = build1 (VIEW_CONVERT_EXPR, TREE_TYPE (*tp), repl); local
951 *tp = vce;
|
| ipa-prop.cc | 5697 bool by_ref, vce; local
5705 vce = false;
5713 vce = true;
5718 if (vce)
|
| tree-ssa-reassoc.cc | 2112 tree vce = build1 (VIEW_CONVERT_EXPR, vec_type, sum_vec); local
2114 gimple *g = gimple_build_assign (lhs, VIEW_CONVERT_EXPR, vce);
2124 tree vce = build1 (VIEW_CONVERT_EXPR, vec_type, local
2127 gimple *g = gimple_build_assign (lhs, VIEW_CONVERT_EXPR, vce);
|
