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Searched refs:vce_dpm_enable_mask (Results 1 - 7 of 7) sorted by relevancy

/src/sys/external/bsd/drm2/dist/drm/amd/powerplay/hwmgr/
smu7_hwmgr.h	`166 uint32_t vce_dpm_enable_mask; member in struct:smu7_dpmlevel_enable_mask`
vega10_hwmgr.h	`176 uint32_t vce_dpm_enable_mask; member in struct:vega10_dpmlevel_enable_mask`
vega12_hwmgr.h	`155 uint32_t vce_dpm_enable_mask; member in struct:vega12_dpmlevel_enable_mask`
vega20_hwmgr.h	`208 uint32_t vce_dpm_enable_mask; member in struct:vega20_dpmlevel_enable_mask`
/src/sys/external/bsd/drm2/dist/drm/radeon/
ci_dpm.h	`110 u32 vce_dpm_enable_mask; member in struct:ci_dpm_level_enable_mask`
radeon_ci_dpm.c	`3998 pi->dpm_level_enable_mask.vce_dpm_enable_mask = 0; 4001 pi->dpm_level_enable_mask.vce_dpm_enable_mask \|= 1 << i; 4010 pi->dpm_level_enable_mask.vce_dpm_enable_mask);`
/src/sys/external/bsd/drm2/dist/drm/amd/powerplay/smumgr/
amdgpu_ci_smumgr.c	`2912 data->dpm_level_enable_mask.vce_dpm_enable_mask = 0; 2916 data->dpm_level_enable_mask.vce_dpm_enable_mask \|= 1 << i; 2921 data->dpm_level_enable_mask.vce_dpm_enable_mask);`

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