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  /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/hwmgr/
hwmgr_ppt.h 62 uint32_t vclk; /* UVD V-clock */ member in struct:phm_ppt_v1_mm_clock_voltage_dependency_record
amdgpu_smu8_hwmgr.c 147 if (clock <= ptable->entries[i].vclk)
155 if (clock >= ptable->entries[i].vclk)
518 (i < uvd_table->count) ? uvd_table->entries[i].vclk : 0;
602 clock = table->entries[level].vclk;
604 clock = table->entries[table->count - 1].vclk;
1393 smu8_ps->uvd_clocks.vclk = ps->uvd_clocks.VCLK;
1697 uint32_t sclk, vclk, dclk, ecclk, tmp, activity_percent; local in function:smu8_read_sensor
1731 vclk = uvd_table->entries[uvd_index].vclk;
    [all...]
smu10_hwmgr.h 99 uint32_t vclk; member in struct:smu10_uvd_clocks
smu7_hwmgr.h 70 uint32_t vclk; member in struct:smu7_uvd_clocks
smu8_hwmgr.h 116 uint32_t vclk; member in struct:smu8_uvd_clocks
vega10_hwmgr.h 98 uint32_t vclk; member in struct:vega10_uvd_clocks
vega20_hwmgr.h 115 uint32_t vclk; member in struct:vega20_uvd_clocks
  /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/inc/
power_state.h 145 uint32_t VCLK;
185 unsigned long vclk; member in struct:pp_clock_engine_request
amdgpu_smu.h 133 uint32_t vclk; member in struct:smu_uvd_clocks
219 uint32_t vclk; member in struct:smu_bios_boot_up_values
hwmgr.h 111 uint32_t vclk; member in struct:phm_uvdclock_voltage_dependency_record
138 uint32_t vclk; member in struct:phm_uvd_clock_voltage_dependency_record
  /src/sys/external/bsd/drm2/dist/drm/radeon/
radeon_rs780_dpm.c 576 if ((new_ps->vclk == old_ps->vclk) &&
583 radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk);
593 if ((new_ps->vclk == old_ps->vclk) &&
600 radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk);
733 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK);
736 rps->vclk = 0;
741 if ((rps->vclk == 0) || (rps->dclk == 0)) {
742 rps->vclk = RS780_DEFAULT_VCLK_FREQ
    [all...]
trinity_dpm.h 71 u32 vclk; member in struct:trinity_uvd_clock_table_entry
radeon_rv770_dpm.c 1443 if ((new_ps->vclk == old_ps->vclk) &&
1450 radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk);
1460 if ((new_ps->vclk == old_ps->vclk) &&
1467 radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk);
2158 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK);
2161 rps->vclk = 0;
2166 if ((rps->vclk == 0) || (rps->dclk == 0)) {
2167 rps->vclk = RV770_DEFAULT_VCLK_FREQ
    [all...]
radeon_trinity_dpm.c 903 if ((rps->vclk == 0) && (rps->dclk == 0))
915 if ((rps1->vclk == rps2->vclk) &&
948 radeon_set_uvd_clocks(rdev, new_rps->vclk, new_rps->dclk);
959 radeon_set_uvd_clocks(rdev, new_rps->vclk, new_rps->dclk);
1463 if ((rps->vclk == pi->sys_info.uvd_clock_table_entries[i].vclk) &&
1697 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK);
1700 rps->vclk = 0;
1938 pi->sys_info.uvd_clock_table_entries[i].vclk
    [all...]
radeon_uvd.c 950 * @vclk: wanted VCLK
960 * @optimal_vclk_div: resulting vclk post divider
967 unsigned vclk, unsigned dclk,
982 vco_min = max(max(vco_min, vclk), dclk);
996 /* calc vclk divider with current vco freq */
997 vclk_div = radeon_uvd_calc_upll_post_div(vco_freq, vclk,
1009 score = vclk - (vco_freq / vclk_div) + dclk - (vco_freq / dclk_div);
radeon_rv6xx_dpm.c 1523 if ((new_ps->vclk == old_ps->vclk) &&
1530 radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk);
1540 if ((new_ps->vclk == old_ps->vclk) &&
1547 radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk);
1808 rps->vclk = RV6XX_DEFAULT_VCLK_FREQ;
1811 rps->vclk = 0;
2020 printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk)
    [all...]
radeon_sumo_dpm.c 829 radeon_set_uvd_clocks(rdev, new_rps->vclk, new_rps->dclk);
845 if ((new_rps->vclk == old_rps->vclk) &&
863 if ((new_rps->vclk == old_rps->vclk) &&
1419 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK);
1422 rps->vclk = 0;
1807 printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
1831 seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk)
    [all...]
radeon_asic.h 413 int r600_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
480 int rv770_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
537 int sumo_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
538 int evergreen_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
751 int si_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
789 int cik_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
radeon_ni_dpm.c 3519 if ((new_ps->vclk == old_ps->vclk) &&
3527 radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk);
3537 if ((new_ps->vclk == old_ps->vclk) &&
3545 radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk);
3908 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK);
3911 rps->vclk = RV770_DEFAULT_VCLK_FREQ;
3914 rps->vclk = 0;
4295 printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk)
    [all...]
  /src/sys/external/bsd/drm2/dist/drm/nouveau/dispnv04/
nouveau_dispnv04_arb.c 198 nv04_update_arb(struct drm_device *dev, int VClk, int bpp,
209 sim_data.pclk_khz = VClk;
256 nouveau_calc_arb(struct drm_device *dev, int vclk, int bpp, int *burst, int *lwm)
261 nv04_update_arb(dev, vclk, bpp, burst, lwm);
hw.h 58 extern void nouveau_calc_arb(struct drm_device *, int vclk, int bpp,
  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_dpm.h 62 u32 vclk; member in struct:amdgpu_ps
164 u32 vclk; member in struct:amdgpu_uvd_clock_voltage_dependency_entry
amdgpu_vi.c 836 static int vi_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk)
841 r = vi_set_uvd_clock(adev, vclk, ixGNB_CLK2_DFS_CNTL, ixGNB_CLK2_STATUS);
849 r = vi_set_uvd_clock(adev, vclk, ixCG_VCLK_CNTL, ixCG_VCLK_STATUS);
amdgpu_kv_dpm.c 924 pi->uvd_level[i].VclkFrequency = cpu_to_be32(table->entries[i].vclk);
929 (u8)kv_get_clk_bypass(adev, table->entries[i].vclk);
934 table->entries[i].vclk, false, &dividers);
2294 pi->video_start = new_rps->dclk || new_rps->vclk ||
2670 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK);
2673 rps->vclk = 0;
2909 printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
3282 *equal = ((cps->vclk == rps->vclk) && (cps->dclk == rps->dclk))
    [all...]
  /src/sys/dev/pci/
pm2fb.c 1565 uint32_t vclk, tmp; local in function:pm2fb_set_dac
1605 vclk = bus_space_read_4(sc->sc_memt, sc->sc_regh, PM2_VCLKCTL);
1607 vclk & 0xfffffffc);
1643 uint32_t vclk; local in function:pm2vfb_set_dac
1684 vclk = bus_space_read_4(sc->sc_memt, sc->sc_regh, PM2_VCLKCTL);
1686 vclk & 0xfffffffc);

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