1 /* $NetBSD: amdgpu_vega12_processpptables.c,v 1.2 2021/12/18 23:45:26 riastradh Exp $ */ 2 3 /* 4 * Copyright 2017 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 */ 25 #include <sys/cdefs.h> 26 __KERNEL_RCSID(0, "$NetBSD: amdgpu_vega12_processpptables.c,v 1.2 2021/12/18 23:45:26 riastradh Exp $"); 27 28 #include <linux/module.h> 29 #include <linux/slab.h> 30 #include <linux/fb.h> 31 32 #include "vega12/smu9_driver_if.h" 33 #include "vega12_processpptables.h" 34 #include "ppatomfwctrl.h" 35 #include "atomfirmware.h" 36 #include "pp_debug.h" 37 #include "cgs_common.h" 38 #include "vega12_pptable.h" 39 40 static void set_hw_cap(struct pp_hwmgr *hwmgr, bool enable, 41 enum phm_platform_caps cap) 42 { 43 if (enable) 44 phm_cap_set(hwmgr->platform_descriptor.platformCaps, cap); 45 else 46 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, cap); 47 } 48 49 static const void *get_powerplay_table(struct pp_hwmgr *hwmgr) 50 { 51 int index = GetIndexIntoMasterDataTable(powerplayinfo); 52 53 u16 size; 54 u8 frev, crev; 55 const void *table_address = hwmgr->soft_pp_table; 56 57 if (!table_address) { 58 table_address = (ATOM_Vega12_POWERPLAYTABLE *) 59 smu_atom_get_data_table(hwmgr->adev, index, 60 &size, &frev, &crev); 61 62 hwmgr->soft_pp_table = table_address; /*Cache the result in RAM.*/ 63 hwmgr->soft_pp_table_size = size; 64 } 65 66 return table_address; 67 } 68 69 static int check_powerplay_tables( 70 struct pp_hwmgr *hwmgr, 71 const ATOM_Vega12_POWERPLAYTABLE *powerplay_table) 72 { 73 PP_ASSERT_WITH_CODE((powerplay_table->sHeader.format_revision >= 74 ATOM_VEGA12_TABLE_REVISION_VEGA12), 75 "Unsupported PPTable format!", return -1); 76 PP_ASSERT_WITH_CODE(powerplay_table->sHeader.structuresize > 0, 77 "Invalid PowerPlay Table!", return -1); 78 79 return 0; 80 } 81 82 static int set_platform_caps(struct pp_hwmgr *hwmgr, uint32_t powerplay_caps) 83 { 84 set_hw_cap( 85 hwmgr, 86 0 != (powerplay_caps & ATOM_VEGA12_PP_PLATFORM_CAP_POWERPLAY), 87 PHM_PlatformCaps_PowerPlaySupport); 88 89 set_hw_cap( 90 hwmgr, 91 0 != (powerplay_caps & ATOM_VEGA12_PP_PLATFORM_CAP_SBIOSPOWERSOURCE), 92 PHM_PlatformCaps_BiosPowerSourceControl); 93 94 set_hw_cap( 95 hwmgr, 96 0 != (powerplay_caps & ATOM_VEGA12_PP_PLATFORM_CAP_BACO), 97 PHM_PlatformCaps_BACO); 98 99 set_hw_cap( 100 hwmgr, 101 0 != (powerplay_caps & ATOM_VEGA12_PP_PLATFORM_CAP_BAMACO), 102 PHM_PlatformCaps_BAMACO); 103 104 return 0; 105 } 106 107 static int append_vbios_pptable(struct pp_hwmgr *hwmgr, PPTable_t *ppsmc_pptable) 108 { 109 struct pp_atomfwctrl_smc_dpm_parameters smc_dpm_table; 110 111 PP_ASSERT_WITH_CODE( 112 pp_atomfwctrl_get_smc_dpm_information(hwmgr, &smc_dpm_table) == 0, 113 "[appendVbiosPPTable] Failed to retrieve Smc Dpm Table from VBIOS!", 114 return -1); 115 116 ppsmc_pptable->Liquid1_I2C_address = smc_dpm_table.liquid1_i2c_address; 117 ppsmc_pptable->Liquid2_I2C_address = smc_dpm_table.liquid2_i2c_address; 118 ppsmc_pptable->Vr_I2C_address = smc_dpm_table.vr_i2c_address; 119 ppsmc_pptable->Plx_I2C_address = smc_dpm_table.plx_i2c_address; 120 121 ppsmc_pptable->Liquid_I2C_LineSCL = smc_dpm_table.liquid_i2c_linescl; 122 ppsmc_pptable->Liquid_I2C_LineSDA = smc_dpm_table.liquid_i2c_linesda; 123 ppsmc_pptable->Vr_I2C_LineSCL = smc_dpm_table.vr_i2c_linescl; 124 ppsmc_pptable->Vr_I2C_LineSDA = smc_dpm_table.vr_i2c_linesda; 125 126 ppsmc_pptable->Plx_I2C_LineSCL = smc_dpm_table.plx_i2c_linescl; 127 ppsmc_pptable->Plx_I2C_LineSDA = smc_dpm_table.plx_i2c_linesda; 128 ppsmc_pptable->VrSensorPresent = smc_dpm_table.vrsensorpresent; 129 ppsmc_pptable->LiquidSensorPresent = smc_dpm_table.liquidsensorpresent; 130 131 ppsmc_pptable->MaxVoltageStepGfx = smc_dpm_table.maxvoltagestepgfx; 132 ppsmc_pptable->MaxVoltageStepSoc = smc_dpm_table.maxvoltagestepsoc; 133 134 ppsmc_pptable->VddGfxVrMapping = smc_dpm_table.vddgfxvrmapping; 135 ppsmc_pptable->VddSocVrMapping = smc_dpm_table.vddsocvrmapping; 136 ppsmc_pptable->VddMem0VrMapping = smc_dpm_table.vddmem0vrmapping; 137 ppsmc_pptable->VddMem1VrMapping = smc_dpm_table.vddmem1vrmapping; 138 139 ppsmc_pptable->GfxUlvPhaseSheddingMask = smc_dpm_table.gfxulvphasesheddingmask; 140 ppsmc_pptable->SocUlvPhaseSheddingMask = smc_dpm_table.soculvphasesheddingmask; 141 142 ppsmc_pptable->GfxMaxCurrent = smc_dpm_table.gfxmaxcurrent; 143 ppsmc_pptable->GfxOffset = smc_dpm_table.gfxoffset; 144 ppsmc_pptable->Padding_TelemetryGfx = smc_dpm_table.padding_telemetrygfx; 145 146 ppsmc_pptable->SocMaxCurrent = smc_dpm_table.socmaxcurrent; 147 ppsmc_pptable->SocOffset = smc_dpm_table.socoffset; 148 ppsmc_pptable->Padding_TelemetrySoc = smc_dpm_table.padding_telemetrysoc; 149 150 ppsmc_pptable->Mem0MaxCurrent = smc_dpm_table.mem0maxcurrent; 151 ppsmc_pptable->Mem0Offset = smc_dpm_table.mem0offset; 152 ppsmc_pptable->Padding_TelemetryMem0 = smc_dpm_table.padding_telemetrymem0; 153 154 ppsmc_pptable->Mem1MaxCurrent = smc_dpm_table.mem1maxcurrent; 155 ppsmc_pptable->Mem1Offset = smc_dpm_table.mem1offset; 156 ppsmc_pptable->Padding_TelemetryMem1 = smc_dpm_table.padding_telemetrymem1; 157 158 ppsmc_pptable->AcDcGpio = smc_dpm_table.acdcgpio; 159 ppsmc_pptable->AcDcPolarity = smc_dpm_table.acdcpolarity; 160 ppsmc_pptable->VR0HotGpio = smc_dpm_table.vr0hotgpio; 161 ppsmc_pptable->VR0HotPolarity = smc_dpm_table.vr0hotpolarity; 162 163 ppsmc_pptable->VR1HotGpio = smc_dpm_table.vr1hotgpio; 164 ppsmc_pptable->VR1HotPolarity = smc_dpm_table.vr1hotpolarity; 165 ppsmc_pptable->Padding1 = smc_dpm_table.padding1; 166 ppsmc_pptable->Padding2 = smc_dpm_table.padding2; 167 168 ppsmc_pptable->LedPin0 = smc_dpm_table.ledpin0; 169 ppsmc_pptable->LedPin1 = smc_dpm_table.ledpin1; 170 ppsmc_pptable->LedPin2 = smc_dpm_table.ledpin2; 171 172 ppsmc_pptable->PllGfxclkSpreadEnabled = smc_dpm_table.pllgfxclkspreadenabled; 173 ppsmc_pptable->PllGfxclkSpreadPercent = smc_dpm_table.pllgfxclkspreadpercent; 174 ppsmc_pptable->PllGfxclkSpreadFreq = smc_dpm_table.pllgfxclkspreadfreq; 175 176 ppsmc_pptable->UclkSpreadEnabled = 0; 177 ppsmc_pptable->UclkSpreadPercent = smc_dpm_table.uclkspreadpercent; 178 ppsmc_pptable->UclkSpreadFreq = smc_dpm_table.uclkspreadfreq; 179 180 ppsmc_pptable->SocclkSpreadEnabled = 0; 181 ppsmc_pptable->SocclkSpreadPercent = smc_dpm_table.socclkspreadpercent; 182 ppsmc_pptable->SocclkSpreadFreq = smc_dpm_table.socclkspreadfreq; 183 184 ppsmc_pptable->AcgGfxclkSpreadEnabled = smc_dpm_table.acggfxclkspreadenabled; 185 ppsmc_pptable->AcgGfxclkSpreadPercent = smc_dpm_table.acggfxclkspreadpercent; 186 ppsmc_pptable->AcgGfxclkSpreadFreq = smc_dpm_table.acggfxclkspreadfreq; 187 188 ppsmc_pptable->Vr2_I2C_address = smc_dpm_table.Vr2_I2C_address; 189 190 ppsmc_pptable->Vr2_I2C_address = smc_dpm_table.Vr2_I2C_address; 191 192 return 0; 193 } 194 195 #define VEGA12_ENGINECLOCK_HARDMAX 198000 196 static int init_powerplay_table_information( 197 struct pp_hwmgr *hwmgr, 198 const ATOM_Vega12_POWERPLAYTABLE *powerplay_table) 199 { 200 struct phm_ppt_v3_information *pptable_information = 201 (struct phm_ppt_v3_information *)hwmgr->pptable; 202 uint32_t disable_power_control = 0; 203 int result; 204 205 hwmgr->thermal_controller.ucType = powerplay_table->ucThermalControllerType; 206 pptable_information->uc_thermal_controller_type = powerplay_table->ucThermalControllerType; 207 208 set_hw_cap(hwmgr, 209 ATOM_VEGA12_PP_THERMALCONTROLLER_NONE != hwmgr->thermal_controller.ucType, 210 PHM_PlatformCaps_ThermalController); 211 212 phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_MicrocodeFanControl); 213 214 if (le32_to_cpu(powerplay_table->ODSettingsMax[ATOM_VEGA12_ODSETTING_GFXCLKFMAX]) > VEGA12_ENGINECLOCK_HARDMAX) 215 hwmgr->platform_descriptor.overdriveLimit.engineClock = VEGA12_ENGINECLOCK_HARDMAX; 216 else 217 hwmgr->platform_descriptor.overdriveLimit.engineClock = 218 le32_to_cpu(powerplay_table->ODSettingsMax[ATOM_VEGA12_ODSETTING_GFXCLKFMAX]); 219 hwmgr->platform_descriptor.overdriveLimit.memoryClock = 220 le32_to_cpu(powerplay_table->ODSettingsMax[ATOM_VEGA12_ODSETTING_UCLKFMAX]); 221 222 phm_copy_overdrive_settings_limits_array(hwmgr, 223 &pptable_information->od_settings_max, 224 powerplay_table->ODSettingsMax, 225 ATOM_VEGA12_ODSETTING_COUNT); 226 phm_copy_overdrive_settings_limits_array(hwmgr, 227 &pptable_information->od_settings_min, 228 powerplay_table->ODSettingsMin, 229 ATOM_VEGA12_ODSETTING_COUNT); 230 231 /* hwmgr->platformDescriptor.minOverdriveVDDC = 0; 232 hwmgr->platformDescriptor.maxOverdriveVDDC = 0; 233 hwmgr->platformDescriptor.overdriveVDDCStep = 0; */ 234 235 if (hwmgr->platform_descriptor.overdriveLimit.engineClock > 0 236 && hwmgr->platform_descriptor.overdriveLimit.memoryClock > 0) 237 phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_ACOverdriveSupport); 238 239 pptable_information->us_small_power_limit1 = le16_to_cpu(powerplay_table->usSmallPowerLimit1); 240 pptable_information->us_small_power_limit2 = le16_to_cpu(powerplay_table->usSmallPowerLimit2); 241 pptable_information->us_boost_power_limit = le16_to_cpu(powerplay_table->usBoostPowerLimit); 242 pptable_information->us_od_turbo_power_limit = le16_to_cpu(powerplay_table->usODTurboPowerLimit); 243 pptable_information->us_od_powersave_power_limit = le16_to_cpu(powerplay_table->usODPowerSavePowerLimit); 244 245 pptable_information->us_software_shutdown_temp = le16_to_cpu(powerplay_table->usSoftwareShutdownTemp); 246 247 hwmgr->platform_descriptor.TDPODLimit = le32_to_cpu(powerplay_table->ODSettingsMax[ATOM_VEGA12_ODSETTING_POWERPERCENTAGE]); 248 249 disable_power_control = 0; 250 if (!disable_power_control) { 251 /* enable TDP overdrive (PowerControl) feature as well if supported */ 252 if (hwmgr->platform_descriptor.TDPODLimit) 253 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 254 PHM_PlatformCaps_PowerControl); 255 } 256 257 phm_copy_clock_limits_array(hwmgr, &pptable_information->power_saving_clock_max, powerplay_table->PowerSavingClockMax, ATOM_VEGA12_PPCLOCK_COUNT); 258 phm_copy_clock_limits_array(hwmgr, &pptable_information->power_saving_clock_min, powerplay_table->PowerSavingClockMin, ATOM_VEGA12_PPCLOCK_COUNT); 259 260 pptable_information->smc_pptable = (PPTable_t *)kmalloc(sizeof(PPTable_t), GFP_KERNEL); 261 if (pptable_information->smc_pptable == NULL) 262 return -ENOMEM; 263 264 memcpy(pptable_information->smc_pptable, &(powerplay_table->smcPPTable), sizeof(PPTable_t)); 265 266 result = append_vbios_pptable(hwmgr, (pptable_information->smc_pptable)); 267 268 return result; 269 } 270 271 int vega12_pp_tables_initialize(struct pp_hwmgr *hwmgr) 272 { 273 int result = 0; 274 const ATOM_Vega12_POWERPLAYTABLE *powerplay_table; 275 276 hwmgr->pptable = kzalloc(sizeof(struct phm_ppt_v3_information), GFP_KERNEL); 277 PP_ASSERT_WITH_CODE((hwmgr->pptable != NULL), 278 "Failed to allocate hwmgr->pptable!", return -ENOMEM); 279 280 powerplay_table = get_powerplay_table(hwmgr); 281 PP_ASSERT_WITH_CODE((powerplay_table != NULL), 282 "Missing PowerPlay Table!", return -1); 283 284 result = check_powerplay_tables(hwmgr, powerplay_table); 285 PP_ASSERT_WITH_CODE((result == 0), 286 "check_powerplay_tables failed", return result); 287 288 result = set_platform_caps(hwmgr, 289 le32_to_cpu(powerplay_table->ulPlatformCaps)); 290 PP_ASSERT_WITH_CODE((result == 0), 291 "set_platform_caps failed", return result); 292 293 result = init_powerplay_table_information(hwmgr, powerplay_table); 294 PP_ASSERT_WITH_CODE((result == 0), 295 "init_powerplay_table_information failed", return result); 296 297 return result; 298 } 299 300 static int vega12_pp_tables_uninitialize(struct pp_hwmgr *hwmgr) 301 { 302 struct phm_ppt_v3_information *pp_table_info = 303 (struct phm_ppt_v3_information *)(hwmgr->pptable); 304 305 kfree(pp_table_info->power_saving_clock_max); 306 pp_table_info->power_saving_clock_max = NULL; 307 308 kfree(pp_table_info->power_saving_clock_min); 309 pp_table_info->power_saving_clock_min = NULL; 310 311 kfree(pp_table_info->od_settings_max); 312 pp_table_info->od_settings_max = NULL; 313 314 kfree(pp_table_info->od_settings_min); 315 pp_table_info->od_settings_min = NULL; 316 317 kfree(pp_table_info->smc_pptable); 318 pp_table_info->smc_pptable = NULL; 319 320 kfree(hwmgr->pptable); 321 hwmgr->pptable = NULL; 322 323 return 0; 324 } 325 326 const struct pp_table_func vega12_pptable_funcs = { 327 .pptable_init = vega12_pp_tables_initialize, 328 .pptable_fini = vega12_pp_tables_uninitialize, 329 }; 330 331 #if 0 332 static uint32_t make_classification_flags(struct pp_hwmgr *hwmgr, 333 uint16_t classification, uint16_t classification2) 334 { 335 uint32_t result = 0; 336 337 if (classification & ATOM_PPLIB_CLASSIFICATION_BOOT) 338 result |= PP_StateClassificationFlag_Boot; 339 340 if (classification & ATOM_PPLIB_CLASSIFICATION_THERMAL) 341 result |= PP_StateClassificationFlag_Thermal; 342 343 if (classification & ATOM_PPLIB_CLASSIFICATION_LIMITEDPOWERSOURCE) 344 result |= PP_StateClassificationFlag_LimitedPowerSource; 345 346 if (classification & ATOM_PPLIB_CLASSIFICATION_REST) 347 result |= PP_StateClassificationFlag_Rest; 348 349 if (classification & ATOM_PPLIB_CLASSIFICATION_FORCED) 350 result |= PP_StateClassificationFlag_Forced; 351 352 if (classification & ATOM_PPLIB_CLASSIFICATION_ACPI) 353 result |= PP_StateClassificationFlag_ACPI; 354 355 if (classification2 & ATOM_PPLIB_CLASSIFICATION2_LIMITEDPOWERSOURCE_2) 356 result |= PP_StateClassificationFlag_LimitedPowerSource_2; 357 358 return result; 359 } 360 361 int vega12_get_powerplay_table_entry(struct pp_hwmgr *hwmgr, 362 uint32_t entry_index, struct pp_power_state *power_state, 363 int (*call_back_func)(struct pp_hwmgr *, void *, 364 struct pp_power_state *, void *, uint32_t)) 365 { 366 int result = 0; 367 const ATOM_Vega12_State_Array *state_arrays; 368 const ATOM_Vega12_State *state_entry; 369 const ATOM_Vega12_POWERPLAYTABLE *pp_table = 370 get_powerplay_table(hwmgr); 371 372 PP_ASSERT_WITH_CODE(pp_table, "Missing PowerPlay Table!", 373 return -1;); 374 power_state->classification.bios_index = entry_index; 375 376 if (pp_table->sHeader.format_revision >= 377 ATOM_Vega12_TABLE_REVISION_VEGA12) { 378 state_arrays = (ATOM_Vega12_State_Array *) 379 (((unsigned long)pp_table) + 380 le16_to_cpu(pp_table->usStateArrayOffset)); 381 382 PP_ASSERT_WITH_CODE(pp_table->usStateArrayOffset > 0, 383 "Invalid PowerPlay Table State Array Offset.", 384 return -1); 385 PP_ASSERT_WITH_CODE(state_arrays->ucNumEntries > 0, 386 "Invalid PowerPlay Table State Array.", 387 return -1); 388 PP_ASSERT_WITH_CODE((entry_index <= state_arrays->ucNumEntries), 389 "Invalid PowerPlay Table State Array Entry.", 390 return -1); 391 392 state_entry = &(state_arrays->states[entry_index]); 393 394 result = call_back_func(hwmgr, (void *)state_entry, power_state, 395 (void *)pp_table, 396 make_classification_flags(hwmgr, 397 le16_to_cpu(state_entry->usClassification), 398 le16_to_cpu(state_entry->usClassification2))); 399 } 400 401 if (!result && (power_state->classification.flags & 402 PP_StateClassificationFlag_Boot)) 403 result = hwmgr->hwmgr_func->patch_boot_state(hwmgr, &(power_state->hardware)); 404 405 return result; 406 } 407 #endif 408
Indexes created Wed Oct 01 15:09:59 GMT 2025