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      1 /*	$NetBSD: amdgpu_vegam_smumgr.c,v 1.2 2021/12/18 23:45:27 riastradh Exp $	*/
      2 
      3 /*
      4  * Copyright 2017 Advanced Micro Devices, Inc.
      5  *
      6  * Permission is hereby granted, free of charge, to any person obtaining a
      7  * copy of this software and associated documentation files (the "Software"),
      8  * to deal in the Software without restriction, including without limitation
      9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
     10  * and/or sell copies of the Software, and to permit persons to whom the
     11  * Software is furnished to do so, subject to the following conditions:
     12  *
     13  * The above copyright notice and this permission notice shall be included in
     14  * all copies or substantial portions of the Software.
     15  *
     16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
     17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
     18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
     19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
     20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
     21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
     22  * OTHER DEALINGS IN THE SOFTWARE.
     23  *
     24  */
     25 #include <sys/cdefs.h>
     26 __KERNEL_RCSID(0, "$NetBSD: amdgpu_vegam_smumgr.c,v 1.2 2021/12/18 23:45:27 riastradh Exp $");
     27 
     28 #include "pp_debug.h"
     29 #include "smumgr.h"
     30 #include "smu_ucode_xfer_vi.h"
     31 #include "vegam_smumgr.h"
     32 #include "smu/smu_7_1_3_d.h"
     33 #include "smu/smu_7_1_3_sh_mask.h"
     34 #include "gmc/gmc_8_1_d.h"
     35 #include "gmc/gmc_8_1_sh_mask.h"
     36 #include "oss/oss_3_0_d.h"
     37 #include "gca/gfx_8_0_d.h"
     38 #include "bif/bif_5_0_d.h"
     39 #include "bif/bif_5_0_sh_mask.h"
     40 #include "ppatomctrl.h"
     41 #include "cgs_common.h"
     42 #include "smu7_ppsmc.h"
     43 
     44 #include "smu7_dyn_defaults.h"
     45 
     46 #include "smu7_hwmgr.h"
     47 #include "hardwaremanager.h"
     48 #include "atombios.h"
     49 #include "pppcielanes.h"
     50 
     51 #include "dce/dce_11_2_d.h"
     52 #include "dce/dce_11_2_sh_mask.h"
     53 
     54 #define PPVEGAM_TARGETACTIVITY_DFLT                     50
     55 
     56 #define VOLTAGE_VID_OFFSET_SCALE1   625
     57 #define VOLTAGE_VID_OFFSET_SCALE2   100
     58 #define POWERTUNE_DEFAULT_SET_MAX    1
     59 #define VDDC_VDDCI_DELTA            200
     60 #define MC_CG_ARB_FREQ_F1           0x0b
     61 
     62 #define STRAP_ASIC_RO_LSB    2168
     63 #define STRAP_ASIC_RO_MSB    2175
     64 
     65 #define PPSMC_MSG_ApplyAvfsCksOffVoltage      ((uint16_t) 0x415)
     66 #define PPSMC_MSG_EnableModeSwitchRLCNotification  ((uint16_t) 0x305)
     67 
     68 static const struct vegam_pt_defaults
     69 vegam_power_tune_data_set_array[POWERTUNE_DEFAULT_SET_MAX] = {
     70 	/* sviLoadLIneEn, SviLoadLineVddC, TDC_VDDC_ThrottleReleaseLimitPerc, TDC_MAWt,
     71 	 * TdcWaterfallCtl, DTEAmbientTempBase, DisplayCac, BAPM_TEMP_GRADIENT */
     72 	{ 1, 0xF, 0xFD, 0x19, 5, 45, 0, 0xB0000,
     73 	{ 0x79, 0x253, 0x25D, 0xAE, 0x72, 0x80, 0x83, 0x86, 0x6F, 0xC8, 0xC9, 0xC9, 0x2F, 0x4D, 0x61},
     74 	{ 0x17C, 0x172, 0x180, 0x1BC, 0x1B3, 0x1BD, 0x206, 0x200, 0x203, 0x25D, 0x25A, 0x255, 0x2C3, 0x2C5, 0x2B4 } },
     75 };
     76 
     77 static const sclkFcwRange_t Range_Table[NUM_SCLK_RANGE] = {
     78 			{VCO_2_4, POSTDIV_DIV_BY_16,  75, 160, 112},
     79 			{VCO_3_6, POSTDIV_DIV_BY_16, 112, 224, 160},
     80 			{VCO_2_4, POSTDIV_DIV_BY_8,   75, 160, 112},
     81 			{VCO_3_6, POSTDIV_DIV_BY_8,  112, 224, 160},
     82 			{VCO_2_4, POSTDIV_DIV_BY_4,   75, 160, 112},
     83 			{VCO_3_6, POSTDIV_DIV_BY_4,  112, 216, 160},
     84 			{VCO_2_4, POSTDIV_DIV_BY_2,   75, 160, 108},
     85 			{VCO_3_6, POSTDIV_DIV_BY_2,  112, 216, 160} };
     86 
     87 static int vegam_smu_init(struct pp_hwmgr *hwmgr)
     88 {
     89 	struct vegam_smumgr *smu_data;
     90 
     91 	smu_data = kzalloc(sizeof(struct vegam_smumgr), GFP_KERNEL);
     92 	if (smu_data == NULL)
     93 		return -ENOMEM;
     94 
     95 	hwmgr->smu_backend = smu_data;
     96 
     97 	if (smu7_init(hwmgr)) {
     98 		kfree(smu_data);
     99 		return -EINVAL;
    100 	}
    101 
    102 	return 0;
    103 }
    104 
    105 static int vegam_start_smu_in_protection_mode(struct pp_hwmgr *hwmgr)
    106 {
    107 	int result = 0;
    108 
    109 	/* Wait for smc boot up */
    110 	/* PHM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(smumgr, SMC_IND, RCU_UC_EVENTS, boot_seq_done, 0) */
    111 
    112 	/* Assert reset */
    113 	PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
    114 					SMC_SYSCON_RESET_CNTL, rst_reg, 1);
    115 
    116 	result = smu7_upload_smu_firmware_image(hwmgr);
    117 	if (result != 0)
    118 		return result;
    119 
    120 	/* Clear status */
    121 	cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixSMU_STATUS, 0);
    122 
    123 	PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
    124 					SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 0);
    125 
    126 	/* De-assert reset */
    127 	PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
    128 					SMC_SYSCON_RESET_CNTL, rst_reg, 0);
    129 
    130 
    131 	PHM_WAIT_VFPF_INDIRECT_FIELD(hwmgr, SMC_IND, RCU_UC_EVENTS, INTERRUPTS_ENABLED, 1);
    132 
    133 
    134 	/* Call Test SMU message with 0x20000 offset to trigger SMU start */
    135 	smu7_send_msg_to_smc_offset(hwmgr);
    136 
    137 	/* Wait done bit to be set */
    138 	/* Check pass/failed indicator */
    139 
    140 	PHM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(hwmgr, SMC_IND, SMU_STATUS, SMU_DONE, 0);
    141 
    142 	if (1 != PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
    143 						SMU_STATUS, SMU_PASS))
    144 		PP_ASSERT_WITH_CODE(false, "SMU Firmware start failed!", return -1);
    145 
    146 	cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixFIRMWARE_FLAGS, 0);
    147 
    148 	PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
    149 					SMC_SYSCON_RESET_CNTL, rst_reg, 1);
    150 
    151 	PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
    152 					SMC_SYSCON_RESET_CNTL, rst_reg, 0);
    153 
    154 	/* Wait for firmware to initialize */
    155 	PHM_WAIT_VFPF_INDIRECT_FIELD(hwmgr, SMC_IND, FIRMWARE_FLAGS, INTERRUPTS_ENABLED, 1);
    156 
    157 	return result;
    158 }
    159 
    160 static int vegam_start_smu_in_non_protection_mode(struct pp_hwmgr *hwmgr)
    161 {
    162 	int result = 0;
    163 
    164 	/* wait for smc boot up */
    165 	PHM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(hwmgr, SMC_IND, RCU_UC_EVENTS, boot_seq_done, 0);
    166 
    167 	/* Clear firmware interrupt enable flag */
    168 	/* PHM_WRITE_VFPF_INDIRECT_FIELD(pSmuMgr, SMC_IND, SMC_SYSCON_MISC_CNTL, pre_fetcher_en, 1); */
    169 	cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
    170 				ixFIRMWARE_FLAGS, 0);
    171 
    172 	PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
    173 					SMC_SYSCON_RESET_CNTL,
    174 					rst_reg, 1);
    175 
    176 	result = smu7_upload_smu_firmware_image(hwmgr);
    177 	if (result != 0)
    178 		return result;
    179 
    180 	/* Set smc instruct start point at 0x0 */
    181 	smu7_program_jump_on_start(hwmgr);
    182 
    183 	PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
    184 					SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 0);
    185 
    186 	PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
    187 					SMC_SYSCON_RESET_CNTL, rst_reg, 0);
    188 
    189 	/* Wait for firmware to initialize */
    190 
    191 	PHM_WAIT_VFPF_INDIRECT_FIELD(hwmgr, SMC_IND,
    192 					FIRMWARE_FLAGS, INTERRUPTS_ENABLED, 1);
    193 
    194 	return result;
    195 }
    196 
    197 static int vegam_start_smu(struct pp_hwmgr *hwmgr)
    198 {
    199 	int result = 0;
    200 	struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend);
    201 
    202 	/* Only start SMC if SMC RAM is not running */
    203 	if (!smu7_is_smc_ram_running(hwmgr) && hwmgr->not_vf) {
    204 		smu_data->protected_mode = (uint8_t)(PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device,
    205 				CGS_IND_REG__SMC, SMU_FIRMWARE, SMU_MODE));
    206 		smu_data->smu7_data.security_hard_key = (uint8_t)(PHM_READ_VFPF_INDIRECT_FIELD(
    207 				hwmgr->device, CGS_IND_REG__SMC, SMU_FIRMWARE, SMU_SEL));
    208 
    209 		/* Check if SMU is running in protected mode */
    210 		if (smu_data->protected_mode == 0)
    211 			result = vegam_start_smu_in_non_protection_mode(hwmgr);
    212 		else
    213 			result = vegam_start_smu_in_protection_mode(hwmgr);
    214 
    215 		if (result != 0)
    216 			PP_ASSERT_WITH_CODE(0, "Failed to load SMU ucode.", return result);
    217 	}
    218 
    219 	/* Setup SoftRegsStart here for register lookup in case DummyBackEnd is used and ProcessFirmwareHeader is not executed */
    220 	smu7_read_smc_sram_dword(hwmgr,
    221 			SMU7_FIRMWARE_HEADER_LOCATION + offsetof(SMU75_Firmware_Header, SoftRegisters),
    222 			&(smu_data->smu7_data.soft_regs_start),
    223 			0x40000);
    224 
    225 	result = smu7_request_smu_load_fw(hwmgr);
    226 
    227 	return result;
    228 }
    229 
    230 static int vegam_process_firmware_header(struct pp_hwmgr *hwmgr)
    231 {
    232 	struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend);
    233 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
    234 	uint32_t tmp;
    235 	int result;
    236 	bool error = false;
    237 
    238 	result = smu7_read_smc_sram_dword(hwmgr,
    239 			SMU7_FIRMWARE_HEADER_LOCATION +
    240 			offsetof(SMU75_Firmware_Header, DpmTable),
    241 			&tmp, SMC_RAM_END);
    242 
    243 	if (0 == result)
    244 		smu_data->smu7_data.dpm_table_start = tmp;
    245 
    246 	error |= (0 != result);
    247 
    248 	result = smu7_read_smc_sram_dword(hwmgr,
    249 			SMU7_FIRMWARE_HEADER_LOCATION +
    250 			offsetof(SMU75_Firmware_Header, SoftRegisters),
    251 			&tmp, SMC_RAM_END);
    252 
    253 	if (!result) {
    254 		data->soft_regs_start = tmp;
    255 		smu_data->smu7_data.soft_regs_start = tmp;
    256 	}
    257 
    258 	error |= (0 != result);
    259 
    260 	result = smu7_read_smc_sram_dword(hwmgr,
    261 			SMU7_FIRMWARE_HEADER_LOCATION +
    262 			offsetof(SMU75_Firmware_Header, mcRegisterTable),
    263 			&tmp, SMC_RAM_END);
    264 
    265 	if (!result)
    266 		smu_data->smu7_data.mc_reg_table_start = tmp;
    267 
    268 	result = smu7_read_smc_sram_dword(hwmgr,
    269 			SMU7_FIRMWARE_HEADER_LOCATION +
    270 			offsetof(SMU75_Firmware_Header, FanTable),
    271 			&tmp, SMC_RAM_END);
    272 
    273 	if (!result)
    274 		smu_data->smu7_data.fan_table_start = tmp;
    275 
    276 	error |= (0 != result);
    277 
    278 	result = smu7_read_smc_sram_dword(hwmgr,
    279 			SMU7_FIRMWARE_HEADER_LOCATION +
    280 			offsetof(SMU75_Firmware_Header, mcArbDramTimingTable),
    281 			&tmp, SMC_RAM_END);
    282 
    283 	if (!result)
    284 		smu_data->smu7_data.arb_table_start = tmp;
    285 
    286 	error |= (0 != result);
    287 
    288 	result = smu7_read_smc_sram_dword(hwmgr,
    289 			SMU7_FIRMWARE_HEADER_LOCATION +
    290 			offsetof(SMU75_Firmware_Header, Version),
    291 			&tmp, SMC_RAM_END);
    292 
    293 	if (!result)
    294 		hwmgr->microcode_version_info.SMC = tmp;
    295 
    296 	error |= (0 != result);
    297 
    298 	return error ? -1 : 0;
    299 }
    300 
    301 static bool vegam_is_dpm_running(struct pp_hwmgr *hwmgr)
    302 {
    303 	return (1 == PHM_READ_INDIRECT_FIELD(hwmgr->device,
    304 			CGS_IND_REG__SMC, FEATURE_STATUS, VOLTAGE_CONTROLLER_ON))
    305 			? true : false;
    306 }
    307 
    308 static uint32_t vegam_get_mac_definition(uint32_t value)
    309 {
    310 	switch (value) {
    311 	case SMU_MAX_LEVELS_GRAPHICS:
    312 		return SMU75_MAX_LEVELS_GRAPHICS;
    313 	case SMU_MAX_LEVELS_MEMORY:
    314 		return SMU75_MAX_LEVELS_MEMORY;
    315 	case SMU_MAX_LEVELS_LINK:
    316 		return SMU75_MAX_LEVELS_LINK;
    317 	case SMU_MAX_ENTRIES_SMIO:
    318 		return SMU75_MAX_ENTRIES_SMIO;
    319 	case SMU_MAX_LEVELS_VDDC:
    320 		return SMU75_MAX_LEVELS_VDDC;
    321 	case SMU_MAX_LEVELS_VDDGFX:
    322 		return SMU75_MAX_LEVELS_VDDGFX;
    323 	case SMU_MAX_LEVELS_VDDCI:
    324 		return SMU75_MAX_LEVELS_VDDCI;
    325 	case SMU_MAX_LEVELS_MVDD:
    326 		return SMU75_MAX_LEVELS_MVDD;
    327 	case SMU_UVD_MCLK_HANDSHAKE_DISABLE:
    328 		return SMU7_UVD_MCLK_HANDSHAKE_DISABLE |
    329 				SMU7_VCE_MCLK_HANDSHAKE_DISABLE;
    330 	}
    331 
    332 	pr_warn("can't get the mac of %x\n", value);
    333 	return 0;
    334 }
    335 
    336 static int vegam_update_uvd_smc_table(struct pp_hwmgr *hwmgr)
    337 {
    338 	struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend);
    339 	uint32_t mm_boot_level_offset, mm_boot_level_value;
    340 	struct phm_ppt_v1_information *table_info =
    341 			(struct phm_ppt_v1_information *)(hwmgr->pptable);
    342 
    343 	smu_data->smc_state_table.UvdBootLevel = 0;
    344 	if (table_info->mm_dep_table->count > 0)
    345 		smu_data->smc_state_table.UvdBootLevel =
    346 				(uint8_t) (table_info->mm_dep_table->count - 1);
    347 	mm_boot_level_offset = smu_data->smu7_data.dpm_table_start + offsetof(SMU75_Discrete_DpmTable,
    348 						UvdBootLevel);
    349 	mm_boot_level_offset /= 4;
    350 	mm_boot_level_offset *= 4;
    351 	mm_boot_level_value = cgs_read_ind_register(hwmgr->device,
    352 			CGS_IND_REG__SMC, mm_boot_level_offset);
    353 	mm_boot_level_value &= 0x00FFFFFF;
    354 	mm_boot_level_value |= smu_data->smc_state_table.UvdBootLevel << 24;
    355 	cgs_write_ind_register(hwmgr->device,
    356 			CGS_IND_REG__SMC, mm_boot_level_offset, mm_boot_level_value);
    357 
    358 	if (!phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
    359 			PHM_PlatformCaps_UVDDPM) ||
    360 		phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
    361 			PHM_PlatformCaps_StablePState))
    362 		smum_send_msg_to_smc_with_parameter(hwmgr,
    363 				PPSMC_MSG_UVDDPM_SetEnabledMask,
    364 				(uint32_t)(1 << smu_data->smc_state_table.UvdBootLevel));
    365 	return 0;
    366 }
    367 
    368 static int vegam_update_vce_smc_table(struct pp_hwmgr *hwmgr)
    369 {
    370 	struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend);
    371 	uint32_t mm_boot_level_offset, mm_boot_level_value;
    372 	struct phm_ppt_v1_information *table_info =
    373 			(struct phm_ppt_v1_information *)(hwmgr->pptable);
    374 
    375 	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
    376 					PHM_PlatformCaps_StablePState))
    377 		smu_data->smc_state_table.VceBootLevel =
    378 			(uint8_t) (table_info->mm_dep_table->count - 1);
    379 	else
    380 		smu_data->smc_state_table.VceBootLevel = 0;
    381 
    382 	mm_boot_level_offset = smu_data->smu7_data.dpm_table_start +
    383 					offsetof(SMU75_Discrete_DpmTable, VceBootLevel);
    384 	mm_boot_level_offset /= 4;
    385 	mm_boot_level_offset *= 4;
    386 	mm_boot_level_value = cgs_read_ind_register(hwmgr->device,
    387 			CGS_IND_REG__SMC, mm_boot_level_offset);
    388 	mm_boot_level_value &= 0xFF00FFFF;
    389 	mm_boot_level_value |= smu_data->smc_state_table.VceBootLevel << 16;
    390 	cgs_write_ind_register(hwmgr->device,
    391 			CGS_IND_REG__SMC, mm_boot_level_offset, mm_boot_level_value);
    392 
    393 	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_StablePState))
    394 		smum_send_msg_to_smc_with_parameter(hwmgr,
    395 				PPSMC_MSG_VCEDPM_SetEnabledMask,
    396 				(uint32_t)1 << smu_data->smc_state_table.VceBootLevel);
    397 	return 0;
    398 }
    399 
    400 static int vegam_update_bif_smc_table(struct pp_hwmgr *hwmgr)
    401 {
    402 	struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend);
    403 	struct phm_ppt_v1_information *table_info =
    404 			(struct phm_ppt_v1_information *)(hwmgr->pptable);
    405 	struct phm_ppt_v1_pcie_table *pcie_table = table_info->pcie_table;
    406 	int max_entry, i;
    407 
    408 	max_entry = (SMU75_MAX_LEVELS_LINK < pcie_table->count) ?
    409 						SMU75_MAX_LEVELS_LINK :
    410 						pcie_table->count;
    411 	/* Setup BIF_SCLK levels */
    412 	for (i = 0; i < max_entry; i++)
    413 		smu_data->bif_sclk_table[i] = pcie_table->entries[i].pcie_sclk;
    414 	return 0;
    415 }
    416 
    417 static int vegam_update_smc_table(struct pp_hwmgr *hwmgr, uint32_t type)
    418 {
    419 	switch (type) {
    420 	case SMU_UVD_TABLE:
    421 		vegam_update_uvd_smc_table(hwmgr);
    422 		break;
    423 	case SMU_VCE_TABLE:
    424 		vegam_update_vce_smc_table(hwmgr);
    425 		break;
    426 	case SMU_BIF_TABLE:
    427 		vegam_update_bif_smc_table(hwmgr);
    428 		break;
    429 	default:
    430 		break;
    431 	}
    432 	return 0;
    433 }
    434 
    435 static void vegam_initialize_power_tune_defaults(struct pp_hwmgr *hwmgr)
    436 {
    437 	struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend);
    438 	struct  phm_ppt_v1_information *table_info =
    439 			(struct  phm_ppt_v1_information *)(hwmgr->pptable);
    440 
    441 	if (table_info &&
    442 			table_info->cac_dtp_table->usPowerTuneDataSetID <= POWERTUNE_DEFAULT_SET_MAX &&
    443 			table_info->cac_dtp_table->usPowerTuneDataSetID)
    444 		smu_data->power_tune_defaults =
    445 				&vegam_power_tune_data_set_array
    446 				[table_info->cac_dtp_table->usPowerTuneDataSetID - 1];
    447 	else
    448 		smu_data->power_tune_defaults = &vegam_power_tune_data_set_array[0];
    449 
    450 }
    451 
    452 static int vegam_populate_smc_mvdd_table(struct pp_hwmgr *hwmgr,
    453 			SMU75_Discrete_DpmTable *table)
    454 {
    455 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
    456 	uint32_t count, level;
    457 
    458 	if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) {
    459 		count = data->mvdd_voltage_table.count;
    460 		if (count > SMU_MAX_SMIO_LEVELS)
    461 			count = SMU_MAX_SMIO_LEVELS;
    462 		for (level = 0; level < count; level++) {
    463 			table->SmioTable2.Pattern[level].Voltage = PP_HOST_TO_SMC_US(
    464 					data->mvdd_voltage_table.entries[level].value * VOLTAGE_SCALE);
    465 			/* Index into DpmTable.Smio. Drive bits from Smio entry to get this voltage level.*/
    466 			table->SmioTable2.Pattern[level].Smio =
    467 				(uint8_t) level;
    468 			table->Smio[level] |=
    469 				data->mvdd_voltage_table.entries[level].smio_low;
    470 		}
    471 		table->SmioMask2 = data->mvdd_voltage_table.mask_low;
    472 
    473 		table->MvddLevelCount = (uint32_t) PP_HOST_TO_SMC_UL(count);
    474 	}
    475 
    476 	return 0;
    477 }
    478 
    479 static int vegam_populate_smc_vddci_table(struct pp_hwmgr *hwmgr,
    480 					struct SMU75_Discrete_DpmTable *table)
    481 {
    482 	uint32_t count, level;
    483 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
    484 
    485 	count = data->vddci_voltage_table.count;
    486 
    487 	if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control) {
    488 		if (count > SMU_MAX_SMIO_LEVELS)
    489 			count = SMU_MAX_SMIO_LEVELS;
    490 		for (level = 0; level < count; ++level) {
    491 			table->SmioTable1.Pattern[level].Voltage = PP_HOST_TO_SMC_US(
    492 					data->vddci_voltage_table.entries[level].value * VOLTAGE_SCALE);
    493 			table->SmioTable1.Pattern[level].Smio = (uint8_t) level;
    494 
    495 			table->Smio[level] |= data->vddci_voltage_table.entries[level].smio_low;
    496 		}
    497 	}
    498 
    499 	table->SmioMask1 = data->vddci_voltage_table.mask_low;
    500 
    501 	return 0;
    502 }
    503 
    504 static int vegam_populate_cac_table(struct pp_hwmgr *hwmgr,
    505 		struct SMU75_Discrete_DpmTable *table)
    506 {
    507 	uint32_t count;
    508 	uint8_t index;
    509 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
    510 	struct phm_ppt_v1_information *table_info =
    511 			(struct phm_ppt_v1_information *)(hwmgr->pptable);
    512 	struct phm_ppt_v1_voltage_lookup_table *lookup_table =
    513 			table_info->vddc_lookup_table;
    514 	/* tables is already swapped, so in order to use the value from it,
    515 	 * we need to swap it back.
    516 	 * We are populating vddc CAC data to BapmVddc table
    517 	 * in split and merged mode
    518 	 */
    519 	for (count = 0; count < lookup_table->count; count++) {
    520 		index = phm_get_voltage_index(lookup_table,
    521 				data->vddc_voltage_table.entries[count].value);
    522 		table->BapmVddcVidLoSidd[count] =
    523 				convert_to_vid(lookup_table->entries[index].us_cac_low);
    524 		table->BapmVddcVidHiSidd[count] =
    525 				convert_to_vid(lookup_table->entries[index].us_cac_mid);
    526 		table->BapmVddcVidHiSidd2[count] =
    527 				convert_to_vid(lookup_table->entries[index].us_cac_high);
    528 	}
    529 
    530 	return 0;
    531 }
    532 
    533 static int vegam_populate_smc_voltage_tables(struct pp_hwmgr *hwmgr,
    534 		struct SMU75_Discrete_DpmTable *table)
    535 {
    536 	vegam_populate_smc_vddci_table(hwmgr, table);
    537 	vegam_populate_smc_mvdd_table(hwmgr, table);
    538 	vegam_populate_cac_table(hwmgr, table);
    539 
    540 	return 0;
    541 }
    542 
    543 static int vegam_populate_ulv_level(struct pp_hwmgr *hwmgr,
    544 		struct SMU75_Discrete_Ulv *state)
    545 {
    546 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
    547 	struct phm_ppt_v1_information *table_info =
    548 			(struct phm_ppt_v1_information *)(hwmgr->pptable);
    549 
    550 	state->CcPwrDynRm = 0;
    551 	state->CcPwrDynRm1 = 0;
    552 
    553 	state->VddcOffset = (uint16_t) table_info->us_ulv_voltage_offset;
    554 	state->VddcOffsetVid = (uint8_t)(table_info->us_ulv_voltage_offset *
    555 			VOLTAGE_VID_OFFSET_SCALE2 / VOLTAGE_VID_OFFSET_SCALE1);
    556 
    557 	state->VddcPhase = data->vddc_phase_shed_control ^ 0x3;
    558 
    559 	CONVERT_FROM_HOST_TO_SMC_UL(state->CcPwrDynRm);
    560 	CONVERT_FROM_HOST_TO_SMC_UL(state->CcPwrDynRm1);
    561 	CONVERT_FROM_HOST_TO_SMC_US(state->VddcOffset);
    562 
    563 	return 0;
    564 }
    565 
    566 static int vegam_populate_ulv_state(struct pp_hwmgr *hwmgr,
    567 		struct SMU75_Discrete_DpmTable *table)
    568 {
    569 	return vegam_populate_ulv_level(hwmgr, &table->Ulv);
    570 }
    571 
    572 static int vegam_populate_smc_link_level(struct pp_hwmgr *hwmgr,
    573 		struct SMU75_Discrete_DpmTable *table)
    574 {
    575 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
    576 	struct vegam_smumgr *smu_data =
    577 			(struct vegam_smumgr *)(hwmgr->smu_backend);
    578 	struct smu7_dpm_table *dpm_table = &data->dpm_table;
    579 	int i;
    580 
    581 	/* Index (dpm_table->pcie_speed_table.count)
    582 	 * is reserved for PCIE boot level. */
    583 	for (i = 0; i <= dpm_table->pcie_speed_table.count; i++) {
    584 		table->LinkLevel[i].PcieGenSpeed  =
    585 				(uint8_t)dpm_table->pcie_speed_table.dpm_levels[i].value;
    586 		table->LinkLevel[i].PcieLaneCount = (uint8_t)encode_pcie_lane_width(
    587 				dpm_table->pcie_speed_table.dpm_levels[i].param1);
    588 		table->LinkLevel[i].EnabledForActivity = 1;
    589 		table->LinkLevel[i].SPC = (uint8_t)(data->pcie_spc_cap & 0xff);
    590 		table->LinkLevel[i].DownThreshold = PP_HOST_TO_SMC_UL(5);
    591 		table->LinkLevel[i].UpThreshold = PP_HOST_TO_SMC_UL(30);
    592 	}
    593 
    594 	smu_data->smc_state_table.LinkLevelCount =
    595 			(uint8_t)dpm_table->pcie_speed_table.count;
    596 
    597 /* To Do move to hwmgr */
    598 	data->dpm_level_enable_mask.pcie_dpm_enable_mask =
    599 			phm_get_dpm_level_enable_mask_value(&dpm_table->pcie_speed_table);
    600 
    601 	return 0;
    602 }
    603 
    604 static int vegam_get_dependency_volt_by_clk(struct pp_hwmgr *hwmgr,
    605 		struct phm_ppt_v1_clock_voltage_dependency_table *dep_table,
    606 		uint32_t clock, SMU_VoltageLevel *voltage, uint32_t *mvdd)
    607 {
    608 	uint32_t i;
    609 	uint16_t vddci;
    610 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
    611 
    612 	*voltage = *mvdd = 0;
    613 
    614 	/* clock - voltage dependency table is empty table */
    615 	if (dep_table->count == 0)
    616 		return -EINVAL;
    617 
    618 	for (i = 0; i < dep_table->count; i++) {
    619 		/* find first sclk bigger than request */
    620 		if (dep_table->entries[i].clk >= clock) {
    621 			*voltage |= (dep_table->entries[i].vddc *
    622 					VOLTAGE_SCALE) << VDDC_SHIFT;
    623 			if (SMU7_VOLTAGE_CONTROL_NONE == data->vddci_control)
    624 				*voltage |= (data->vbios_boot_state.vddci_bootup_value *
    625 						VOLTAGE_SCALE) << VDDCI_SHIFT;
    626 			else if (dep_table->entries[i].vddci)
    627 				*voltage |= (dep_table->entries[i].vddci *
    628 						VOLTAGE_SCALE) << VDDCI_SHIFT;
    629 			else {
    630 				vddci = phm_find_closest_vddci(&(data->vddci_voltage_table),
    631 						(dep_table->entries[i].vddc -
    632 								(uint16_t)VDDC_VDDCI_DELTA));
    633 				*voltage |= (vddci * VOLTAGE_SCALE) << VDDCI_SHIFT;
    634 			}
    635 
    636 			if (SMU7_VOLTAGE_CONTROL_NONE == data->mvdd_control)
    637 				*mvdd = data->vbios_boot_state.mvdd_bootup_value *
    638 					VOLTAGE_SCALE;
    639 			else if (dep_table->entries[i].mvdd)
    640 				*mvdd = (uint32_t) dep_table->entries[i].mvdd *
    641 					VOLTAGE_SCALE;
    642 
    643 			*voltage |= 1 << PHASES_SHIFT;
    644 			return 0;
    645 		}
    646 	}
    647 
    648 	/* sclk is bigger than max sclk in the dependence table */
    649 	*voltage |= (dep_table->entries[i - 1].vddc * VOLTAGE_SCALE) << VDDC_SHIFT;
    650 	vddci = phm_find_closest_vddci(&(data->vddci_voltage_table),
    651 			(dep_table->entries[i - 1].vddc -
    652 					(uint16_t)VDDC_VDDCI_DELTA));
    653 
    654 	if (SMU7_VOLTAGE_CONTROL_NONE == data->vddci_control)
    655 		*voltage |= (data->vbios_boot_state.vddci_bootup_value *
    656 				VOLTAGE_SCALE) << VDDCI_SHIFT;
    657 	else if (dep_table->entries[i - 1].vddci)
    658 		*voltage |= (dep_table->entries[i - 1].vddci *
    659 				VOLTAGE_SCALE) << VDDC_SHIFT;
    660 	else
    661 		*voltage |= (vddci * VOLTAGE_SCALE) << VDDCI_SHIFT;
    662 
    663 	if (SMU7_VOLTAGE_CONTROL_NONE == data->mvdd_control)
    664 		*mvdd = data->vbios_boot_state.mvdd_bootup_value * VOLTAGE_SCALE;
    665 	else if (dep_table->entries[i].mvdd)
    666 		*mvdd = (uint32_t) dep_table->entries[i - 1].mvdd * VOLTAGE_SCALE;
    667 
    668 	return 0;
    669 }
    670 
    671 static void vegam_get_sclk_range_table(struct pp_hwmgr *hwmgr,
    672 				   SMU75_Discrete_DpmTable  *table)
    673 {
    674 	struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend);
    675 	uint32_t i, ref_clk;
    676 
    677 	struct pp_atom_ctrl_sclk_range_table range_table_from_vbios = { { {0} } };
    678 
    679 	ref_clk = amdgpu_asic_get_xclk((struct amdgpu_device *)hwmgr->adev);
    680 
    681 	if (0 == atomctrl_get_smc_sclk_range_table(hwmgr, &range_table_from_vbios)) {
    682 		for (i = 0; i < NUM_SCLK_RANGE; i++) {
    683 			table->SclkFcwRangeTable[i].vco_setting =
    684 					range_table_from_vbios.entry[i].ucVco_setting;
    685 			table->SclkFcwRangeTable[i].postdiv =
    686 					range_table_from_vbios.entry[i].ucPostdiv;
    687 			table->SclkFcwRangeTable[i].fcw_pcc =
    688 					range_table_from_vbios.entry[i].usFcw_pcc;
    689 
    690 			table->SclkFcwRangeTable[i].fcw_trans_upper =
    691 					range_table_from_vbios.entry[i].usFcw_trans_upper;
    692 			table->SclkFcwRangeTable[i].fcw_trans_lower =
    693 					range_table_from_vbios.entry[i].usRcw_trans_lower;
    694 
    695 			CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_pcc);
    696 			CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_trans_upper);
    697 			CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_trans_lower);
    698 		}
    699 		return;
    700 	}
    701 
    702 	for (i = 0; i < NUM_SCLK_RANGE; i++) {
    703 		smu_data->range_table[i].trans_lower_frequency =
    704 				(ref_clk * Range_Table[i].fcw_trans_lower) >> Range_Table[i].postdiv;
    705 		smu_data->range_table[i].trans_upper_frequency =
    706 				(ref_clk * Range_Table[i].fcw_trans_upper) >> Range_Table[i].postdiv;
    707 
    708 		table->SclkFcwRangeTable[i].vco_setting = Range_Table[i].vco_setting;
    709 		table->SclkFcwRangeTable[i].postdiv = Range_Table[i].postdiv;
    710 		table->SclkFcwRangeTable[i].fcw_pcc = Range_Table[i].fcw_pcc;
    711 
    712 		table->SclkFcwRangeTable[i].fcw_trans_upper = Range_Table[i].fcw_trans_upper;
    713 		table->SclkFcwRangeTable[i].fcw_trans_lower = Range_Table[i].fcw_trans_lower;
    714 
    715 		CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_pcc);
    716 		CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_trans_upper);
    717 		CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_trans_lower);
    718 	}
    719 }
    720 
    721 static int vegam_calculate_sclk_params(struct pp_hwmgr *hwmgr,
    722 		uint32_t clock, SMU_SclkSetting *sclk_setting)
    723 {
    724 	struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend);
    725 	const SMU75_Discrete_DpmTable *table = &(smu_data->smc_state_table);
    726 	struct pp_atomctrl_clock_dividers_ai dividers;
    727 	uint32_t ref_clock;
    728 	uint32_t pcc_target_percent, pcc_target_freq, ss_target_percent, ss_target_freq;
    729 	uint8_t i;
    730 	int result;
    731 	uint64_t temp;
    732 
    733 	sclk_setting->SclkFrequency = clock;
    734 	/* get the engine clock dividers for this clock value */
    735 	result = atomctrl_get_engine_pll_dividers_ai(hwmgr, clock,  &dividers);
    736 	if (result == 0) {
    737 		sclk_setting->Fcw_int = dividers.usSclk_fcw_int;
    738 		sclk_setting->Fcw_frac = dividers.usSclk_fcw_frac;
    739 		sclk_setting->Pcc_fcw_int = dividers.usPcc_fcw_int;
    740 		sclk_setting->PllRange = dividers.ucSclkPllRange;
    741 		sclk_setting->Sclk_slew_rate = 0x400;
    742 		sclk_setting->Pcc_up_slew_rate = dividers.usPcc_fcw_slew_frac;
    743 		sclk_setting->Pcc_down_slew_rate = 0xffff;
    744 		sclk_setting->SSc_En = dividers.ucSscEnable;
    745 		sclk_setting->Fcw1_int = dividers.usSsc_fcw1_int;
    746 		sclk_setting->Fcw1_frac = dividers.usSsc_fcw1_frac;
    747 		sclk_setting->Sclk_ss_slew_rate = dividers.usSsc_fcw_slew_frac;
    748 		return result;
    749 	}
    750 
    751 	ref_clock = amdgpu_asic_get_xclk((struct amdgpu_device *)hwmgr->adev);
    752 
    753 	for (i = 0; i < NUM_SCLK_RANGE; i++) {
    754 		if (clock > smu_data->range_table[i].trans_lower_frequency
    755 		&& clock <= smu_data->range_table[i].trans_upper_frequency) {
    756 			sclk_setting->PllRange = i;
    757 			break;
    758 		}
    759 	}
    760 
    761 	sclk_setting->Fcw_int = (uint16_t)
    762 			((clock << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv) /
    763 					ref_clock);
    764 	temp = clock << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv;
    765 	temp <<= 0x10;
    766 	do_div(temp, ref_clock);
    767 	sclk_setting->Fcw_frac = temp & 0xffff;
    768 
    769 	pcc_target_percent = 10; /*  Hardcode 10% for now. */
    770 	pcc_target_freq = clock - (clock * pcc_target_percent / 100);
    771 	sclk_setting->Pcc_fcw_int = (uint16_t)
    772 			((pcc_target_freq << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv) /
    773 					ref_clock);
    774 
    775 	ss_target_percent = 2; /*  Hardcode 2% for now. */
    776 	sclk_setting->SSc_En = 0;
    777 	if (ss_target_percent) {
    778 		sclk_setting->SSc_En = 1;
    779 		ss_target_freq = clock - (clock * ss_target_percent / 100);
    780 		sclk_setting->Fcw1_int = (uint16_t)
    781 				((ss_target_freq << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv) /
    782 						ref_clock);
    783 		temp = ss_target_freq << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv;
    784 		temp <<= 0x10;
    785 		do_div(temp, ref_clock);
    786 		sclk_setting->Fcw1_frac = temp & 0xffff;
    787 	}
    788 
    789 	return 0;
    790 }
    791 
    792 static uint8_t vegam_get_sleep_divider_id_from_clock(uint32_t clock,
    793 		uint32_t clock_insr)
    794 {
    795 	uint8_t i;
    796 	uint32_t temp;
    797 	uint32_t min = max(clock_insr, (uint32_t)SMU7_MINIMUM_ENGINE_CLOCK);
    798 
    799 	PP_ASSERT_WITH_CODE((clock >= min),
    800 			"Engine clock can't satisfy stutter requirement!",
    801 			return 0);
    802 	for (i = 31;  ; i--) {
    803 		temp = clock / (i + 1);
    804 
    805 		if (temp >= min || i == 0)
    806 			break;
    807 	}
    808 	return i;
    809 }
    810 
    811 static int vegam_populate_single_graphic_level(struct pp_hwmgr *hwmgr,
    812 		uint32_t clock, struct SMU75_Discrete_GraphicsLevel *level)
    813 {
    814 	int result;
    815 	/* PP_Clocks minClocks; */
    816 	uint32_t mvdd;
    817 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
    818 	struct phm_ppt_v1_information *table_info =
    819 			(struct phm_ppt_v1_information *)(hwmgr->pptable);
    820 	SMU_SclkSetting curr_sclk_setting = { 0 };
    821 
    822 	result = vegam_calculate_sclk_params(hwmgr, clock, &curr_sclk_setting);
    823 
    824 	/* populate graphics levels */
    825 	result = vegam_get_dependency_volt_by_clk(hwmgr,
    826 			table_info->vdd_dep_on_sclk, clock,
    827 			&level->MinVoltage, &mvdd);
    828 
    829 	PP_ASSERT_WITH_CODE((0 == result),
    830 			"can not find VDDC voltage value for "
    831 			"VDDC engine clock dependency table",
    832 			return result);
    833 	level->ActivityLevel = (uint16_t)(SclkDPMTuning_VEGAM >> DPMTuning_Activity_Shift);
    834 
    835 	level->CcPwrDynRm = 0;
    836 	level->CcPwrDynRm1 = 0;
    837 	level->EnabledForActivity = 0;
    838 	level->EnabledForThrottle = 1;
    839 	level->VoltageDownHyst = 0;
    840 	level->PowerThrottle = 0;
    841 	data->display_timing.min_clock_in_sr = hwmgr->display_config->min_core_set_clock_in_sr;
    842 
    843 	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep))
    844 		level->DeepSleepDivId = vegam_get_sleep_divider_id_from_clock(clock,
    845 								hwmgr->display_config->min_core_set_clock_in_sr);
    846 
    847 	level->SclkSetting = curr_sclk_setting;
    848 
    849 	CONVERT_FROM_HOST_TO_SMC_UL(level->MinVoltage);
    850 	CONVERT_FROM_HOST_TO_SMC_UL(level->CcPwrDynRm);
    851 	CONVERT_FROM_HOST_TO_SMC_UL(level->CcPwrDynRm1);
    852 	CONVERT_FROM_HOST_TO_SMC_US(level->ActivityLevel);
    853 	CONVERT_FROM_HOST_TO_SMC_UL(level->SclkSetting.SclkFrequency);
    854 	CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Fcw_int);
    855 	CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Fcw_frac);
    856 	CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Pcc_fcw_int);
    857 	CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Sclk_slew_rate);
    858 	CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Pcc_up_slew_rate);
    859 	CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Pcc_down_slew_rate);
    860 	CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Fcw1_int);
    861 	CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Fcw1_frac);
    862 	CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Sclk_ss_slew_rate);
    863 	return 0;
    864 }
    865 
    866 static int vegam_populate_all_graphic_levels(struct pp_hwmgr *hwmgr)
    867 {
    868 	struct smu7_hwmgr *hw_data = (struct smu7_hwmgr *)(hwmgr->backend);
    869 	struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend);
    870 	struct smu7_dpm_table *dpm_table = &hw_data->dpm_table;
    871 	struct phm_ppt_v1_information *table_info =
    872 			(struct phm_ppt_v1_information *)(hwmgr->pptable);
    873 	struct phm_ppt_v1_pcie_table *pcie_table = table_info->pcie_table;
    874 	uint8_t pcie_entry_cnt = (uint8_t) hw_data->dpm_table.pcie_speed_table.count;
    875 	int result = 0;
    876 	uint32_t array = smu_data->smu7_data.dpm_table_start +
    877 			offsetof(SMU75_Discrete_DpmTable, GraphicsLevel);
    878 	uint32_t array_size = sizeof(struct SMU75_Discrete_GraphicsLevel) *
    879 			SMU75_MAX_LEVELS_GRAPHICS;
    880 	struct SMU75_Discrete_GraphicsLevel *levels =
    881 			smu_data->smc_state_table.GraphicsLevel;
    882 	uint32_t i, max_entry;
    883 	uint8_t hightest_pcie_level_enabled = 0,
    884 		lowest_pcie_level_enabled = 0,
    885 		mid_pcie_level_enabled = 0,
    886 		count = 0;
    887 
    888 	vegam_get_sclk_range_table(hwmgr, &(smu_data->smc_state_table));
    889 
    890 	for (i = 0; i < dpm_table->sclk_table.count; i++) {
    891 
    892 		result = vegam_populate_single_graphic_level(hwmgr,
    893 				dpm_table->sclk_table.dpm_levels[i].value,
    894 				&(smu_data->smc_state_table.GraphicsLevel[i]));
    895 		if (result)
    896 			return result;
    897 
    898 		levels[i].UpHyst = (uint8_t)
    899 				(SclkDPMTuning_VEGAM >> DPMTuning_Uphyst_Shift);
    900 		levels[i].DownHyst = (uint8_t)
    901 				(SclkDPMTuning_VEGAM >> DPMTuning_Downhyst_Shift);
    902 		/* Making sure only DPM level 0-1 have Deep Sleep Div ID populated. */
    903 		if (i > 1)
    904 			levels[i].DeepSleepDivId = 0;
    905 	}
    906 	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
    907 					PHM_PlatformCaps_SPLLShutdownSupport))
    908 		smu_data->smc_state_table.GraphicsLevel[0].SclkSetting.SSc_En = 0;
    909 
    910 	smu_data->smc_state_table.GraphicsDpmLevelCount =
    911 			(uint8_t)dpm_table->sclk_table.count;
    912 	hw_data->dpm_level_enable_mask.sclk_dpm_enable_mask =
    913 			phm_get_dpm_level_enable_mask_value(&dpm_table->sclk_table);
    914 
    915 	for (i = 0; i < dpm_table->sclk_table.count; i++)
    916 		levels[i].EnabledForActivity =
    917 				(hw_data->dpm_level_enable_mask.sclk_dpm_enable_mask >> i) & 0x1;
    918 
    919 	if (pcie_table != NULL) {
    920 		PP_ASSERT_WITH_CODE((1 <= pcie_entry_cnt),
    921 				"There must be 1 or more PCIE levels defined in PPTable.",
    922 				return -EINVAL);
    923 		max_entry = pcie_entry_cnt - 1;
    924 		for (i = 0; i < dpm_table->sclk_table.count; i++)
    925 			levels[i].pcieDpmLevel =
    926 					(uint8_t) ((i < max_entry) ? i : max_entry);
    927 	} else {
    928 		while (hw_data->dpm_level_enable_mask.pcie_dpm_enable_mask &&
    929 				((hw_data->dpm_level_enable_mask.pcie_dpm_enable_mask &
    930 						(1 << (hightest_pcie_level_enabled + 1))) != 0))
    931 			hightest_pcie_level_enabled++;
    932 
    933 		while (hw_data->dpm_level_enable_mask.pcie_dpm_enable_mask &&
    934 				((hw_data->dpm_level_enable_mask.pcie_dpm_enable_mask &
    935 						(1 << lowest_pcie_level_enabled)) == 0))
    936 			lowest_pcie_level_enabled++;
    937 
    938 		while ((count < hightest_pcie_level_enabled) &&
    939 				((hw_data->dpm_level_enable_mask.pcie_dpm_enable_mask &
    940 						(1 << (lowest_pcie_level_enabled + 1 + count))) == 0))
    941 			count++;
    942 
    943 		mid_pcie_level_enabled = (lowest_pcie_level_enabled + 1 + count) <
    944 				hightest_pcie_level_enabled ?
    945 						(lowest_pcie_level_enabled + 1 + count) :
    946 						hightest_pcie_level_enabled;
    947 
    948 		/* set pcieDpmLevel to hightest_pcie_level_enabled */
    949 		for (i = 2; i < dpm_table->sclk_table.count; i++)
    950 			levels[i].pcieDpmLevel = hightest_pcie_level_enabled;
    951 
    952 		/* set pcieDpmLevel to lowest_pcie_level_enabled */
    953 		levels[0].pcieDpmLevel = lowest_pcie_level_enabled;
    954 
    955 		/* set pcieDpmLevel to mid_pcie_level_enabled */
    956 		levels[1].pcieDpmLevel = mid_pcie_level_enabled;
    957 	}
    958 	/* level count will send to smc once at init smc table and never change */
    959 	result = smu7_copy_bytes_to_smc(hwmgr, array, (uint8_t *)levels,
    960 			(uint32_t)array_size, SMC_RAM_END);
    961 
    962 	return result;
    963 }
    964 
    965 static int vegam_calculate_mclk_params(struct pp_hwmgr *hwmgr,
    966 		uint32_t clock, struct SMU75_Discrete_MemoryLevel *mem_level)
    967 {
    968 	struct pp_atomctrl_memory_clock_param_ai mpll_param;
    969 
    970 	PP_ASSERT_WITH_CODE(!atomctrl_get_memory_pll_dividers_ai(hwmgr,
    971 			clock, &mpll_param),
    972 			"Failed to retrieve memory pll parameter.",
    973 			return -EINVAL);
    974 
    975 	mem_level->MclkFrequency = (uint32_t)mpll_param.ulClock;
    976 	mem_level->Fcw_int = (uint16_t)mpll_param.ulMclk_fcw_int;
    977 	mem_level->Fcw_frac = (uint16_t)mpll_param.ulMclk_fcw_frac;
    978 	mem_level->Postdiv = (uint8_t)mpll_param.ulPostDiv;
    979 
    980 	return 0;
    981 }
    982 
    983 static int vegam_populate_single_memory_level(struct pp_hwmgr *hwmgr,
    984 		uint32_t clock, struct SMU75_Discrete_MemoryLevel *mem_level)
    985 {
    986 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
    987 	struct phm_ppt_v1_information *table_info =
    988 			(struct phm_ppt_v1_information *)(hwmgr->pptable);
    989 	int result = 0;
    990 	uint32_t mclk_stutter_mode_threshold = 60000;
    991 
    992 
    993 	if (table_info->vdd_dep_on_mclk) {
    994 		result = vegam_get_dependency_volt_by_clk(hwmgr,
    995 				table_info->vdd_dep_on_mclk, clock,
    996 				&mem_level->MinVoltage, &mem_level->MinMvdd);
    997 		PP_ASSERT_WITH_CODE(!result,
    998 				"can not find MinVddc voltage value from memory "
    999 				"VDDC voltage dependency table", return result);
   1000 	}
   1001 
   1002 	result = vegam_calculate_mclk_params(hwmgr, clock, mem_level);
   1003 	PP_ASSERT_WITH_CODE(!result,
   1004 			"Failed to calculate mclk params.",
   1005 			return -EINVAL);
   1006 
   1007 	mem_level->EnabledForThrottle = 1;
   1008 	mem_level->EnabledForActivity = 0;
   1009 	mem_level->VoltageDownHyst = 0;
   1010 	mem_level->ActivityLevel = (uint16_t)
   1011 			(MemoryDPMTuning_VEGAM >> DPMTuning_Activity_Shift);
   1012 	mem_level->StutterEnable = false;
   1013 	mem_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
   1014 
   1015 	data->display_timing.num_existing_displays = hwmgr->display_config->num_display;
   1016 	data->display_timing.vrefresh = hwmgr->display_config->vrefresh;
   1017 
   1018 	if (mclk_stutter_mode_threshold &&
   1019 		(clock <= mclk_stutter_mode_threshold) &&
   1020 		(PHM_READ_FIELD(hwmgr->device, DPG_PIPE_STUTTER_CONTROL,
   1021 				STUTTER_ENABLE) & 0x1))
   1022 		mem_level->StutterEnable = true;
   1023 
   1024 	if (!result) {
   1025 		CONVERT_FROM_HOST_TO_SMC_UL(mem_level->MinMvdd);
   1026 		CONVERT_FROM_HOST_TO_SMC_UL(mem_level->MclkFrequency);
   1027 		CONVERT_FROM_HOST_TO_SMC_US(mem_level->Fcw_int);
   1028 		CONVERT_FROM_HOST_TO_SMC_US(mem_level->Fcw_frac);
   1029 		CONVERT_FROM_HOST_TO_SMC_US(mem_level->ActivityLevel);
   1030 		CONVERT_FROM_HOST_TO_SMC_UL(mem_level->MinVoltage);
   1031 	}
   1032 
   1033 	return result;
   1034 }
   1035 
   1036 static int vegam_populate_all_memory_levels(struct pp_hwmgr *hwmgr)
   1037 {
   1038 	struct smu7_hwmgr *hw_data = (struct smu7_hwmgr *)(hwmgr->backend);
   1039 	struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend);
   1040 	struct smu7_dpm_table *dpm_table = &hw_data->dpm_table;
   1041 	int result;
   1042 	/* populate MCLK dpm table to SMU7 */
   1043 	uint32_t array = smu_data->smu7_data.dpm_table_start +
   1044 			offsetof(SMU75_Discrete_DpmTable, MemoryLevel);
   1045 	uint32_t array_size = sizeof(SMU75_Discrete_MemoryLevel) *
   1046 			SMU75_MAX_LEVELS_MEMORY;
   1047 	struct SMU75_Discrete_MemoryLevel *levels =
   1048 			smu_data->smc_state_table.MemoryLevel;
   1049 	uint32_t i;
   1050 
   1051 	for (i = 0; i < dpm_table->mclk_table.count; i++) {
   1052 		PP_ASSERT_WITH_CODE((0 != dpm_table->mclk_table.dpm_levels[i].value),
   1053 				"can not populate memory level as memory clock is zero",
   1054 				return -EINVAL);
   1055 		result = vegam_populate_single_memory_level(hwmgr,
   1056 				dpm_table->mclk_table.dpm_levels[i].value,
   1057 				&levels[i]);
   1058 
   1059 		if (result)
   1060 			return result;
   1061 
   1062 		levels[i].UpHyst = (uint8_t)
   1063 				(MemoryDPMTuning_VEGAM >> DPMTuning_Uphyst_Shift);
   1064 		levels[i].DownHyst = (uint8_t)
   1065 				(MemoryDPMTuning_VEGAM >> DPMTuning_Downhyst_Shift);
   1066 	}
   1067 
   1068 	smu_data->smc_state_table.MemoryDpmLevelCount =
   1069 			(uint8_t)dpm_table->mclk_table.count;
   1070 	hw_data->dpm_level_enable_mask.mclk_dpm_enable_mask =
   1071 			phm_get_dpm_level_enable_mask_value(&dpm_table->mclk_table);
   1072 
   1073 	for (i = 0; i < dpm_table->mclk_table.count; i++)
   1074 		levels[i].EnabledForActivity =
   1075 				(hw_data->dpm_level_enable_mask.mclk_dpm_enable_mask >> i) & 0x1;
   1076 
   1077 	levels[dpm_table->mclk_table.count - 1].DisplayWatermark =
   1078 			PPSMC_DISPLAY_WATERMARK_HIGH;
   1079 
   1080 	/* level count will send to smc once at init smc table and never change */
   1081 	result = smu7_copy_bytes_to_smc(hwmgr, array, (uint8_t *)levels,
   1082 			(uint32_t)array_size, SMC_RAM_END);
   1083 
   1084 	return result;
   1085 }
   1086 
   1087 static int vegam_populate_mvdd_value(struct pp_hwmgr *hwmgr,
   1088 		uint32_t mclk, SMIO_Pattern *smio_pat)
   1089 {
   1090 	const struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
   1091 	struct phm_ppt_v1_information *table_info =
   1092 			(struct phm_ppt_v1_information *)(hwmgr->pptable);
   1093 	uint32_t i = 0;
   1094 
   1095 	if (SMU7_VOLTAGE_CONTROL_NONE != data->mvdd_control) {
   1096 		/* find mvdd value which clock is more than request */
   1097 		for (i = 0; i < table_info->vdd_dep_on_mclk->count; i++) {
   1098 			if (mclk <= table_info->vdd_dep_on_mclk->entries[i].clk) {
   1099 				smio_pat->Voltage = data->mvdd_voltage_table.entries[i].value;
   1100 				break;
   1101 			}
   1102 		}
   1103 		PP_ASSERT_WITH_CODE(i < table_info->vdd_dep_on_mclk->count,
   1104 				"MVDD Voltage is outside the supported range.",
   1105 				return -EINVAL);
   1106 	} else
   1107 		return -EINVAL;
   1108 
   1109 	return 0;
   1110 }
   1111 
   1112 static int vegam_populate_smc_acpi_level(struct pp_hwmgr *hwmgr,
   1113 		SMU75_Discrete_DpmTable *table)
   1114 {
   1115 	int result = 0;
   1116 	uint32_t sclk_frequency;
   1117 	const struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
   1118 	struct phm_ppt_v1_information *table_info =
   1119 			(struct phm_ppt_v1_information *)(hwmgr->pptable);
   1120 	SMIO_Pattern vol_level;
   1121 	uint32_t mvdd;
   1122 
   1123 	table->ACPILevel.Flags &= ~PPSMC_SWSTATE_FLAG_DC;
   1124 
   1125 	/* Get MinVoltage and Frequency from DPM0,
   1126 	 * already converted to SMC_UL */
   1127 	sclk_frequency = data->vbios_boot_state.sclk_bootup_value;
   1128 	result = vegam_get_dependency_volt_by_clk(hwmgr,
   1129 			table_info->vdd_dep_on_sclk,
   1130 			sclk_frequency,
   1131 			&table->ACPILevel.MinVoltage, &mvdd);
   1132 	PP_ASSERT_WITH_CODE(!result,
   1133 			"Cannot find ACPI VDDC voltage value "
   1134 			"in Clock Dependency Table",
   1135 			);
   1136 
   1137 	result = vegam_calculate_sclk_params(hwmgr, sclk_frequency,
   1138 			&(table->ACPILevel.SclkSetting));
   1139 	PP_ASSERT_WITH_CODE(!result,
   1140 			"Error retrieving Engine Clock dividers from VBIOS.",
   1141 			return result);
   1142 
   1143 	table->ACPILevel.DeepSleepDivId = 0;
   1144 	table->ACPILevel.CcPwrDynRm = 0;
   1145 	table->ACPILevel.CcPwrDynRm1 = 0;
   1146 
   1147 	CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.Flags);
   1148 	CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.MinVoltage);
   1149 	CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CcPwrDynRm);
   1150 	CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CcPwrDynRm1);
   1151 
   1152 	CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.SclkSetting.SclkFrequency);
   1153 	CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Fcw_int);
   1154 	CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Fcw_frac);
   1155 	CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Pcc_fcw_int);
   1156 	CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Sclk_slew_rate);
   1157 	CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Pcc_up_slew_rate);
   1158 	CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Pcc_down_slew_rate);
   1159 	CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Fcw1_int);
   1160 	CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Fcw1_frac);
   1161 	CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Sclk_ss_slew_rate);
   1162 
   1163 
   1164 	/* Get MinVoltage and Frequency from DPM0, already converted to SMC_UL */
   1165 	table->MemoryACPILevel.MclkFrequency = data->vbios_boot_state.mclk_bootup_value;
   1166 	result = vegam_get_dependency_volt_by_clk(hwmgr,
   1167 			table_info->vdd_dep_on_mclk,
   1168 			table->MemoryACPILevel.MclkFrequency,
   1169 			&table->MemoryACPILevel.MinVoltage, &mvdd);
   1170 	PP_ASSERT_WITH_CODE((0 == result),
   1171 			"Cannot find ACPI VDDCI voltage value "
   1172 			"in Clock Dependency Table",
   1173 			);
   1174 
   1175 	if (!vegam_populate_mvdd_value(hwmgr, 0, &vol_level))
   1176 		table->MemoryACPILevel.MinMvdd = PP_HOST_TO_SMC_UL(vol_level.Voltage);
   1177 	else
   1178 		table->MemoryACPILevel.MinMvdd = 0;
   1179 
   1180 	table->MemoryACPILevel.StutterEnable = false;
   1181 
   1182 	table->MemoryACPILevel.EnabledForThrottle = 0;
   1183 	table->MemoryACPILevel.EnabledForActivity = 0;
   1184 	table->MemoryACPILevel.UpHyst = 0;
   1185 	table->MemoryACPILevel.DownHyst = 100;
   1186 	table->MemoryACPILevel.VoltageDownHyst = 0;
   1187 	table->MemoryACPILevel.ActivityLevel =
   1188 		PP_HOST_TO_SMC_US(data->current_profile_setting.mclk_activity);
   1189 
   1190 	CONVERT_FROM_HOST_TO_SMC_UL(table->MemoryACPILevel.MclkFrequency);
   1191 	CONVERT_FROM_HOST_TO_SMC_UL(table->MemoryACPILevel.MinVoltage);
   1192 
   1193 	return result;
   1194 }
   1195 
   1196 static int vegam_populate_smc_vce_level(struct pp_hwmgr *hwmgr,
   1197 		SMU75_Discrete_DpmTable *table)
   1198 {
   1199 	int result = -EINVAL;
   1200 	uint8_t count;
   1201 	struct pp_atomctrl_clock_dividers_vi dividers;
   1202 	struct phm_ppt_v1_information *table_info =
   1203 			(struct phm_ppt_v1_information *)(hwmgr->pptable);
   1204 	struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
   1205 			table_info->mm_dep_table;
   1206 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
   1207 	uint32_t vddci;
   1208 
   1209 	table->VceLevelCount = (uint8_t)(mm_table->count);
   1210 	table->VceBootLevel = 0;
   1211 
   1212 	for (count = 0; count < table->VceLevelCount; count++) {
   1213 		table->VceLevel[count].Frequency = mm_table->entries[count].eclk;
   1214 		table->VceLevel[count].MinVoltage = 0;
   1215 		table->VceLevel[count].MinVoltage |=
   1216 				(mm_table->entries[count].vddc * VOLTAGE_SCALE) << VDDC_SHIFT;
   1217 
   1218 		if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control)
   1219 			vddci = (uint32_t)phm_find_closest_vddci(&(data->vddci_voltage_table),
   1220 						mm_table->entries[count].vddc - VDDC_VDDCI_DELTA);
   1221 		else if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->vddci_control)
   1222 			vddci = mm_table->entries[count].vddc - VDDC_VDDCI_DELTA;
   1223 		else
   1224 			vddci = (data->vbios_boot_state.vddci_bootup_value * VOLTAGE_SCALE) << VDDCI_SHIFT;
   1225 
   1226 
   1227 		table->VceLevel[count].MinVoltage |=
   1228 				(vddci * VOLTAGE_SCALE) << VDDCI_SHIFT;
   1229 		table->VceLevel[count].MinVoltage |= 1 << PHASES_SHIFT;
   1230 
   1231 		/*retrieve divider value for VBIOS */
   1232 		result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
   1233 				table->VceLevel[count].Frequency, &dividers);
   1234 		PP_ASSERT_WITH_CODE((0 == result),
   1235 				"can not find divide id for VCE engine clock",
   1236 				return result);
   1237 
   1238 		table->VceLevel[count].Divider = (uint8_t)dividers.pll_post_divider;
   1239 
   1240 		CONVERT_FROM_HOST_TO_SMC_UL(table->VceLevel[count].Frequency);
   1241 		CONVERT_FROM_HOST_TO_SMC_UL(table->VceLevel[count].MinVoltage);
   1242 	}
   1243 	return result;
   1244 }
   1245 
   1246 static int vegam_populate_memory_timing_parameters(struct pp_hwmgr *hwmgr,
   1247 		int32_t eng_clock, int32_t mem_clock,
   1248 		SMU75_Discrete_MCArbDramTimingTableEntry *arb_regs)
   1249 {
   1250 	uint32_t dram_timing;
   1251 	uint32_t dram_timing2;
   1252 	uint32_t burst_time;
   1253 	uint32_t rfsh_rate;
   1254 	uint32_t misc3;
   1255 
   1256 	int result;
   1257 
   1258 	result = atomctrl_set_engine_dram_timings_rv770(hwmgr,
   1259 			eng_clock, mem_clock);
   1260 	PP_ASSERT_WITH_CODE(result == 0,
   1261 			"Error calling VBIOS to set DRAM_TIMING.",
   1262 			return result);
   1263 
   1264 	dram_timing = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING);
   1265 	dram_timing2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2);
   1266 	burst_time = cgs_read_register(hwmgr->device, mmMC_ARB_BURST_TIME);
   1267 	rfsh_rate = cgs_read_register(hwmgr->device, mmMC_ARB_RFSH_RATE);
   1268 	misc3 = cgs_read_register(hwmgr->device, mmMC_ARB_MISC3);
   1269 
   1270 	arb_regs->McArbDramTiming  = PP_HOST_TO_SMC_UL(dram_timing);
   1271 	arb_regs->McArbDramTiming2 = PP_HOST_TO_SMC_UL(dram_timing2);
   1272 	arb_regs->McArbBurstTime   = PP_HOST_TO_SMC_UL(burst_time);
   1273 	arb_regs->McArbRfshRate = PP_HOST_TO_SMC_UL(rfsh_rate);
   1274 	arb_regs->McArbMisc3 = PP_HOST_TO_SMC_UL(misc3);
   1275 
   1276 	return 0;
   1277 }
   1278 
   1279 static int vegam_program_memory_timing_parameters(struct pp_hwmgr *hwmgr)
   1280 {
   1281 	struct smu7_hwmgr *hw_data = (struct smu7_hwmgr *)(hwmgr->backend);
   1282 	struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend);
   1283 	struct SMU75_Discrete_MCArbDramTimingTable arb_regs;
   1284 	uint32_t i, j;
   1285 	int result = 0;
   1286 
   1287 	memset(&arb_regs, 0, sizeof(SMU75_Discrete_MCArbDramTimingTable));
   1288 
   1289 	for (i = 0; i < hw_data->dpm_table.sclk_table.count; i++) {
   1290 		for (j = 0; j < hw_data->dpm_table.mclk_table.count; j++) {
   1291 			result = vegam_populate_memory_timing_parameters(hwmgr,
   1292 					hw_data->dpm_table.sclk_table.dpm_levels[i].value,
   1293 					hw_data->dpm_table.mclk_table.dpm_levels[j].value,
   1294 					&arb_regs.entries[i][j]);
   1295 			if (result)
   1296 				return result;
   1297 		}
   1298 	}
   1299 
   1300 	result = smu7_copy_bytes_to_smc(
   1301 			hwmgr,
   1302 			smu_data->smu7_data.arb_table_start,
   1303 			(uint8_t *)&arb_regs,
   1304 			sizeof(SMU75_Discrete_MCArbDramTimingTable),
   1305 			SMC_RAM_END);
   1306 	return result;
   1307 }
   1308 
   1309 static int vegam_populate_smc_uvd_level(struct pp_hwmgr *hwmgr,
   1310 		struct SMU75_Discrete_DpmTable *table)
   1311 {
   1312 	int result = -EINVAL;
   1313 	uint8_t count;
   1314 	struct pp_atomctrl_clock_dividers_vi dividers;
   1315 	struct phm_ppt_v1_information *table_info =
   1316 			(struct phm_ppt_v1_information *)(hwmgr->pptable);
   1317 	struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
   1318 			table_info->mm_dep_table;
   1319 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
   1320 	uint32_t vddci;
   1321 
   1322 	table->UvdLevelCount = (uint8_t)(mm_table->count);
   1323 	table->UvdBootLevel = 0;
   1324 
   1325 	for (count = 0; count < table->UvdLevelCount; count++) {
   1326 		table->UvdLevel[count].MinVoltage = 0;
   1327 		table->UvdLevel[count].VclkFrequency = mm_table->entries[count].vclk;
   1328 		table->UvdLevel[count].DclkFrequency = mm_table->entries[count].dclk;
   1329 		table->UvdLevel[count].MinVoltage |=
   1330 				(mm_table->entries[count].vddc * VOLTAGE_SCALE) << VDDC_SHIFT;
   1331 
   1332 		if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control)
   1333 			vddci = (uint32_t)phm_find_closest_vddci(&(data->vddci_voltage_table),
   1334 						mm_table->entries[count].vddc - VDDC_VDDCI_DELTA);
   1335 		else if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->vddci_control)
   1336 			vddci = mm_table->entries[count].vddc - VDDC_VDDCI_DELTA;
   1337 		else
   1338 			vddci = (data->vbios_boot_state.vddci_bootup_value * VOLTAGE_SCALE) << VDDCI_SHIFT;
   1339 
   1340 		table->UvdLevel[count].MinVoltage |= (vddci * VOLTAGE_SCALE) << VDDCI_SHIFT;
   1341 		table->UvdLevel[count].MinVoltage |= 1 << PHASES_SHIFT;
   1342 
   1343 		/* retrieve divider value for VBIOS */
   1344 		result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
   1345 				table->UvdLevel[count].VclkFrequency, &dividers);
   1346 		PP_ASSERT_WITH_CODE((0 == result),
   1347 				"can not find divide id for Vclk clock", return result);
   1348 
   1349 		table->UvdLevel[count].VclkDivider = (uint8_t)dividers.pll_post_divider;
   1350 
   1351 		result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
   1352 				table->UvdLevel[count].DclkFrequency, &dividers);
   1353 		PP_ASSERT_WITH_CODE((0 == result),
   1354 				"can not find divide id for Dclk clock", return result);
   1355 
   1356 		table->UvdLevel[count].DclkDivider = (uint8_t)dividers.pll_post_divider;
   1357 
   1358 		CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].VclkFrequency);
   1359 		CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].DclkFrequency);
   1360 		CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].MinVoltage);
   1361 	}
   1362 
   1363 	return result;
   1364 }
   1365 
   1366 static int vegam_populate_smc_boot_level(struct pp_hwmgr *hwmgr,
   1367 		struct SMU75_Discrete_DpmTable *table)
   1368 {
   1369 	int result = 0;
   1370 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
   1371 
   1372 	table->GraphicsBootLevel = 0;
   1373 	table->MemoryBootLevel = 0;
   1374 
   1375 	/* find boot level from dpm table */
   1376 	result = phm_find_boot_level(&(data->dpm_table.sclk_table),
   1377 			data->vbios_boot_state.sclk_bootup_value,
   1378 			(uint32_t *)&(table->GraphicsBootLevel));
   1379 	if (result)
   1380 		return result;
   1381 
   1382 	result = phm_find_boot_level(&(data->dpm_table.mclk_table),
   1383 			data->vbios_boot_state.mclk_bootup_value,
   1384 			(uint32_t *)&(table->MemoryBootLevel));
   1385 
   1386 	if (result)
   1387 		return result;
   1388 
   1389 	table->BootVddc  = data->vbios_boot_state.vddc_bootup_value *
   1390 			VOLTAGE_SCALE;
   1391 	table->BootVddci = data->vbios_boot_state.vddci_bootup_value *
   1392 			VOLTAGE_SCALE;
   1393 	table->BootMVdd  = data->vbios_boot_state.mvdd_bootup_value *
   1394 			VOLTAGE_SCALE;
   1395 
   1396 	CONVERT_FROM_HOST_TO_SMC_US(table->BootVddc);
   1397 	CONVERT_FROM_HOST_TO_SMC_US(table->BootVddci);
   1398 	CONVERT_FROM_HOST_TO_SMC_US(table->BootMVdd);
   1399 
   1400 	return 0;
   1401 }
   1402 
   1403 static int vegam_populate_smc_initial_state(struct pp_hwmgr *hwmgr)
   1404 {
   1405 	struct smu7_hwmgr *hw_data = (struct smu7_hwmgr *)(hwmgr->backend);
   1406 	struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend);
   1407 	struct phm_ppt_v1_information *table_info =
   1408 			(struct phm_ppt_v1_information *)(hwmgr->pptable);
   1409 	uint8_t count, level;
   1410 
   1411 	count = (uint8_t)(table_info->vdd_dep_on_sclk->count);
   1412 
   1413 	for (level = 0; level < count; level++) {
   1414 		if (table_info->vdd_dep_on_sclk->entries[level].clk >=
   1415 				hw_data->vbios_boot_state.sclk_bootup_value) {
   1416 			smu_data->smc_state_table.GraphicsBootLevel = level;
   1417 			break;
   1418 		}
   1419 	}
   1420 
   1421 	count = (uint8_t)(table_info->vdd_dep_on_mclk->count);
   1422 	for (level = 0; level < count; level++) {
   1423 		if (table_info->vdd_dep_on_mclk->entries[level].clk >=
   1424 				hw_data->vbios_boot_state.mclk_bootup_value) {
   1425 			smu_data->smc_state_table.MemoryBootLevel = level;
   1426 			break;
   1427 		}
   1428 	}
   1429 
   1430 	return 0;
   1431 }
   1432 
   1433 static uint16_t scale_fan_gain_settings(uint16_t raw_setting)
   1434 {
   1435 	uint32_t tmp;
   1436 	tmp = raw_setting * 4096 / 100;
   1437 	return (uint16_t)tmp;
   1438 }
   1439 
   1440 static int vegam_populate_bapm_parameters_in_dpm_table(struct pp_hwmgr *hwmgr)
   1441 {
   1442 	struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend);
   1443 
   1444 	const struct vegam_pt_defaults *defaults = smu_data->power_tune_defaults;
   1445 	SMU75_Discrete_DpmTable  *table = &(smu_data->smc_state_table);
   1446 	struct phm_ppt_v1_information *table_info =
   1447 			(struct phm_ppt_v1_information *)(hwmgr->pptable);
   1448 	struct phm_cac_tdp_table *cac_dtp_table = table_info->cac_dtp_table;
   1449 	struct pp_advance_fan_control_parameters *fan_table =
   1450 			&hwmgr->thermal_controller.advanceFanControlParameters;
   1451 	int i, j, k;
   1452 	const uint16_t *pdef1;
   1453 	const uint16_t *pdef2;
   1454 
   1455 	table->DefaultTdp = PP_HOST_TO_SMC_US((uint16_t)(cac_dtp_table->usTDP * 128));
   1456 	table->TargetTdp  = PP_HOST_TO_SMC_US((uint16_t)(cac_dtp_table->usTDP * 128));
   1457 
   1458 	PP_ASSERT_WITH_CODE(cac_dtp_table->usTargetOperatingTemp <= 255,
   1459 				"Target Operating Temp is out of Range!",
   1460 				);
   1461 
   1462 	table->TemperatureLimitEdge = PP_HOST_TO_SMC_US(
   1463 			cac_dtp_table->usTargetOperatingTemp * 256);
   1464 	table->TemperatureLimitHotspot = PP_HOST_TO_SMC_US(
   1465 			cac_dtp_table->usTemperatureLimitHotspot * 256);
   1466 	table->FanGainEdge = PP_HOST_TO_SMC_US(
   1467 			scale_fan_gain_settings(fan_table->usFanGainEdge));
   1468 	table->FanGainHotspot = PP_HOST_TO_SMC_US(
   1469 			scale_fan_gain_settings(fan_table->usFanGainHotspot));
   1470 
   1471 	pdef1 = defaults->BAPMTI_R;
   1472 	pdef2 = defaults->BAPMTI_RC;
   1473 
   1474 	for (i = 0; i < SMU75_DTE_ITERATIONS; i++) {
   1475 		for (j = 0; j < SMU75_DTE_SOURCES; j++) {
   1476 			for (k = 0; k < SMU75_DTE_SINKS; k++) {
   1477 				table->BAPMTI_R[i][j][k] = PP_HOST_TO_SMC_US(*pdef1);
   1478 				table->BAPMTI_RC[i][j][k] = PP_HOST_TO_SMC_US(*pdef2);
   1479 				pdef1++;
   1480 				pdef2++;
   1481 			}
   1482 		}
   1483 	}
   1484 
   1485 	return 0;
   1486 }
   1487 
   1488 static int vegam_populate_clock_stretcher_data_table(struct pp_hwmgr *hwmgr)
   1489 {
   1490 	uint32_t ro, efuse, volt_without_cks, volt_with_cks, value, max, min;
   1491 	struct vegam_smumgr *smu_data =
   1492 			(struct vegam_smumgr *)(hwmgr->smu_backend);
   1493 
   1494 	uint8_t i, stretch_amount, volt_offset = 0;
   1495 	struct phm_ppt_v1_information *table_info =
   1496 			(struct phm_ppt_v1_information *)(hwmgr->pptable);
   1497 	struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table =
   1498 			table_info->vdd_dep_on_sclk;
   1499 	uint32_t mask = (1 << ((STRAP_ASIC_RO_MSB - STRAP_ASIC_RO_LSB) + 1)) - 1;
   1500 
   1501 	stretch_amount = (uint8_t)table_info->cac_dtp_table->usClockStretchAmount;
   1502 
   1503 	atomctrl_read_efuse(hwmgr, STRAP_ASIC_RO_LSB, STRAP_ASIC_RO_MSB,
   1504 			mask, &efuse);
   1505 
   1506 	min = 1200;
   1507 	max = 2500;
   1508 
   1509 	ro = efuse * (max - min) / 255 + min;
   1510 
   1511 	/* Populate Sclk_CKS_masterEn0_7 and Sclk_voltageOffset */
   1512 	for (i = 0; i < sclk_table->count; i++) {
   1513 		smu_data->smc_state_table.Sclk_CKS_masterEn0_7 |=
   1514 				sclk_table->entries[i].cks_enable << i;
   1515 		volt_without_cks = (uint32_t)((2753594000U + (sclk_table->entries[i].clk/100) *
   1516 				136418 - (ro - 70) * 1000000) /
   1517 				(2424180 - (sclk_table->entries[i].clk/100) * 1132925/1000));
   1518 		volt_with_cks = (uint32_t)((2797202000U + sclk_table->entries[i].clk/100 *
   1519 				3232 - (ro - 65) * 1000000) /
   1520 				(2522480 - sclk_table->entries[i].clk/100 * 115764/100));
   1521 
   1522 		if (volt_without_cks >= volt_with_cks)
   1523 			volt_offset = (uint8_t)(((volt_without_cks - volt_with_cks +
   1524 					sclk_table->entries[i].cks_voffset) * 100 + 624) / 625);
   1525 
   1526 		smu_data->smc_state_table.Sclk_voltageOffset[i] = volt_offset;
   1527 	}
   1528 
   1529 	smu_data->smc_state_table.LdoRefSel =
   1530 			(table_info->cac_dtp_table->ucCKS_LDO_REFSEL != 0) ?
   1531 			table_info->cac_dtp_table->ucCKS_LDO_REFSEL : 5;
   1532 	/* Populate CKS Lookup Table */
   1533 	if (!(stretch_amount == 1 || stretch_amount == 2 ||
   1534 	      stretch_amount == 5 || stretch_amount == 3 ||
   1535 	      stretch_amount == 4)) {
   1536 		phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
   1537 				PHM_PlatformCaps_ClockStretcher);
   1538 		PP_ASSERT_WITH_CODE(false,
   1539 				"Stretch Amount in PPTable not supported\n",
   1540 				return -EINVAL);
   1541 	}
   1542 
   1543 	value = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixPWR_CKS_CNTL);
   1544 	value &= 0xFFFFFFFE;
   1545 	cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixPWR_CKS_CNTL, value);
   1546 
   1547 	return 0;
   1548 }
   1549 
   1550 static bool vegam_is_hw_avfs_present(struct pp_hwmgr *hwmgr)
   1551 {
   1552 	uint32_t efuse;
   1553 
   1554 	efuse = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
   1555 			ixSMU_EFUSE_0 + (49 * 4));
   1556 	efuse &= 0x00000001;
   1557 
   1558 	if (efuse)
   1559 		return true;
   1560 
   1561 	return false;
   1562 }
   1563 
   1564 static int vegam_populate_avfs_parameters(struct pp_hwmgr *hwmgr)
   1565 {
   1566 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
   1567 	struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend);
   1568 
   1569 	SMU75_Discrete_DpmTable  *table = &(smu_data->smc_state_table);
   1570 	int result = 0;
   1571 	struct pp_atom_ctrl__avfs_parameters avfs_params = {0};
   1572 	AVFS_meanNsigma_t AVFS_meanNsigma = { {0} };
   1573 	AVFS_Sclk_Offset_t AVFS_SclkOffset = { {0} };
   1574 	uint32_t tmp, i;
   1575 
   1576 	struct phm_ppt_v1_information *table_info =
   1577 			(struct phm_ppt_v1_information *)hwmgr->pptable;
   1578 	struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table =
   1579 			table_info->vdd_dep_on_sclk;
   1580 
   1581 	if (!hwmgr->avfs_supported)
   1582 		return 0;
   1583 
   1584 	result = atomctrl_get_avfs_information(hwmgr, &avfs_params);
   1585 
   1586 	if (0 == result) {
   1587 		table->BTCGB_VDROOP_TABLE[0].a0 =
   1588 				PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSON_a0);
   1589 		table->BTCGB_VDROOP_TABLE[0].a1 =
   1590 				PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSON_a1);
   1591 		table->BTCGB_VDROOP_TABLE[0].a2 =
   1592 				PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSON_a2);
   1593 		table->BTCGB_VDROOP_TABLE[1].a0 =
   1594 				PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a0);
   1595 		table->BTCGB_VDROOP_TABLE[1].a1 =
   1596 				PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a1);
   1597 		table->BTCGB_VDROOP_TABLE[1].a2 =
   1598 				PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a2);
   1599 		table->AVFSGB_FUSE_TABLE[0].m1 =
   1600 				PP_HOST_TO_SMC_UL(avfs_params.ulAVFSGB_FUSE_TABLE_CKSON_m1);
   1601 		table->AVFSGB_FUSE_TABLE[0].m2 =
   1602 				PP_HOST_TO_SMC_US(avfs_params.usAVFSGB_FUSE_TABLE_CKSON_m2);
   1603 		table->AVFSGB_FUSE_TABLE[0].b =
   1604 				PP_HOST_TO_SMC_UL(avfs_params.ulAVFSGB_FUSE_TABLE_CKSON_b);
   1605 		table->AVFSGB_FUSE_TABLE[0].m1_shift = 24;
   1606 		table->AVFSGB_FUSE_TABLE[0].m2_shift = 12;
   1607 		table->AVFSGB_FUSE_TABLE[1].m1 =
   1608 				PP_HOST_TO_SMC_UL(avfs_params.ulAVFSGB_FUSE_TABLE_CKSOFF_m1);
   1609 		table->AVFSGB_FUSE_TABLE[1].m2 =
   1610 				PP_HOST_TO_SMC_US(avfs_params.usAVFSGB_FUSE_TABLE_CKSOFF_m2);
   1611 		table->AVFSGB_FUSE_TABLE[1].b =
   1612 				PP_HOST_TO_SMC_UL(avfs_params.ulAVFSGB_FUSE_TABLE_CKSOFF_b);
   1613 		table->AVFSGB_FUSE_TABLE[1].m1_shift = 24;
   1614 		table->AVFSGB_FUSE_TABLE[1].m2_shift = 12;
   1615 		table->MaxVoltage = PP_HOST_TO_SMC_US(avfs_params.usMaxVoltage_0_25mv);
   1616 		AVFS_meanNsigma.Aconstant[0] =
   1617 				PP_HOST_TO_SMC_UL(avfs_params.ulAVFS_meanNsigma_Acontant0);
   1618 		AVFS_meanNsigma.Aconstant[1] =
   1619 				PP_HOST_TO_SMC_UL(avfs_params.ulAVFS_meanNsigma_Acontant1);
   1620 		AVFS_meanNsigma.Aconstant[2] =
   1621 				PP_HOST_TO_SMC_UL(avfs_params.ulAVFS_meanNsigma_Acontant2);
   1622 		AVFS_meanNsigma.DC_tol_sigma =
   1623 				PP_HOST_TO_SMC_US(avfs_params.usAVFS_meanNsigma_DC_tol_sigma);
   1624 		AVFS_meanNsigma.Platform_mean =
   1625 				PP_HOST_TO_SMC_US(avfs_params.usAVFS_meanNsigma_Platform_mean);
   1626 		AVFS_meanNsigma.PSM_Age_CompFactor =
   1627 				PP_HOST_TO_SMC_US(avfs_params.usPSM_Age_ComFactor);
   1628 		AVFS_meanNsigma.Platform_sigma =
   1629 				PP_HOST_TO_SMC_US(avfs_params.usAVFS_meanNsigma_Platform_sigma);
   1630 
   1631 		for (i = 0; i < sclk_table->count; i++) {
   1632 			AVFS_meanNsigma.Static_Voltage_Offset[i] =
   1633 					(uint8_t)(sclk_table->entries[i].cks_voffset * 100 / 625);
   1634 			AVFS_SclkOffset.Sclk_Offset[i] =
   1635 					PP_HOST_TO_SMC_US((uint16_t)
   1636 							(sclk_table->entries[i].sclk_offset) / 100);
   1637 		}
   1638 
   1639 		result = smu7_read_smc_sram_dword(hwmgr,
   1640 				SMU7_FIRMWARE_HEADER_LOCATION +
   1641 				offsetof(SMU75_Firmware_Header, AvfsMeanNSigma),
   1642 				&tmp, SMC_RAM_END);
   1643 		smu7_copy_bytes_to_smc(hwmgr,
   1644 					tmp,
   1645 					(uint8_t *)&AVFS_meanNsigma,
   1646 					sizeof(AVFS_meanNsigma_t),
   1647 					SMC_RAM_END);
   1648 
   1649 		result = smu7_read_smc_sram_dword(hwmgr,
   1650 				SMU7_FIRMWARE_HEADER_LOCATION +
   1651 				offsetof(SMU75_Firmware_Header, AvfsSclkOffsetTable),
   1652 				&tmp, SMC_RAM_END);
   1653 		smu7_copy_bytes_to_smc(hwmgr,
   1654 					tmp,
   1655 					(uint8_t *)&AVFS_SclkOffset,
   1656 					sizeof(AVFS_Sclk_Offset_t),
   1657 					SMC_RAM_END);
   1658 
   1659 		data->avfs_vdroop_override_setting =
   1660 				(avfs_params.ucEnableGB_VDROOP_TABLE_CKSON << BTCGB0_Vdroop_Enable_SHIFT) |
   1661 				(avfs_params.ucEnableGB_VDROOP_TABLE_CKSOFF << BTCGB1_Vdroop_Enable_SHIFT) |
   1662 				(avfs_params.ucEnableGB_FUSE_TABLE_CKSON << AVFSGB0_Vdroop_Enable_SHIFT) |
   1663 				(avfs_params.ucEnableGB_FUSE_TABLE_CKSOFF << AVFSGB1_Vdroop_Enable_SHIFT);
   1664 		data->apply_avfs_cks_off_voltage =
   1665 				(avfs_params.ucEnableApplyAVFS_CKS_OFF_Voltage == 1) ? true : false;
   1666 	}
   1667 	return result;
   1668 }
   1669 
   1670 static int vegam_populate_vr_config(struct pp_hwmgr *hwmgr,
   1671 		struct SMU75_Discrete_DpmTable *table)
   1672 {
   1673 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
   1674 	struct vegam_smumgr *smu_data =
   1675 			(struct vegam_smumgr *)(hwmgr->smu_backend);
   1676 	uint16_t config;
   1677 
   1678 	config = VR_MERGED_WITH_VDDC;
   1679 	table->VRConfig |= (config << VRCONF_VDDGFX_SHIFT);
   1680 
   1681 	/* Set Vddc Voltage Controller */
   1682 	if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->voltage_control) {
   1683 		config = VR_SVI2_PLANE_1;
   1684 		table->VRConfig |= config;
   1685 	} else {
   1686 		PP_ASSERT_WITH_CODE(false,
   1687 				"VDDC should be on SVI2 control in merged mode!",
   1688 				);
   1689 	}
   1690 	/* Set Vddci Voltage Controller */
   1691 	if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->vddci_control) {
   1692 		config = VR_SVI2_PLANE_2;  /* only in merged mode */
   1693 		table->VRConfig |= (config << VRCONF_VDDCI_SHIFT);
   1694 	} else if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control) {
   1695 		config = VR_SMIO_PATTERN_1;
   1696 		table->VRConfig |= (config << VRCONF_VDDCI_SHIFT);
   1697 	} else {
   1698 		config = VR_STATIC_VOLTAGE;
   1699 		table->VRConfig |= (config << VRCONF_VDDCI_SHIFT);
   1700 	}
   1701 	/* Set Mvdd Voltage Controller */
   1702 	if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->mvdd_control) {
   1703 		if (config != VR_SVI2_PLANE_2) {
   1704 			config = VR_SVI2_PLANE_2;
   1705 			table->VRConfig |= (config << VRCONF_MVDD_SHIFT);
   1706 			cgs_write_ind_register(hwmgr->device,
   1707 					CGS_IND_REG__SMC,
   1708 					smu_data->smu7_data.soft_regs_start +
   1709 					offsetof(SMU75_SoftRegisters, AllowMvddSwitch),
   1710 					0x1);
   1711 		} else {
   1712 			PP_ASSERT_WITH_CODE(false,
   1713 					"SVI2 Plane 2 is already taken, set MVDD as Static",);
   1714 			config = VR_STATIC_VOLTAGE;
   1715 			table->VRConfig = (config << VRCONF_MVDD_SHIFT);
   1716 		}
   1717 	} else if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) {
   1718 		config = VR_SMIO_PATTERN_2;
   1719 		table->VRConfig = (config << VRCONF_MVDD_SHIFT);
   1720 		cgs_write_ind_register(hwmgr->device,
   1721 				CGS_IND_REG__SMC,
   1722 				smu_data->smu7_data.soft_regs_start +
   1723 				offsetof(SMU75_SoftRegisters, AllowMvddSwitch),
   1724 				0x1);
   1725 	} else {
   1726 		config = VR_STATIC_VOLTAGE;
   1727 		table->VRConfig |= (config << VRCONF_MVDD_SHIFT);
   1728 	}
   1729 
   1730 	return 0;
   1731 }
   1732 
   1733 static int vegam_populate_svi_load_line(struct pp_hwmgr *hwmgr)
   1734 {
   1735 	struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend);
   1736 	const struct vegam_pt_defaults *defaults = smu_data->power_tune_defaults;
   1737 
   1738 	smu_data->power_tune_table.SviLoadLineEn = defaults->SviLoadLineEn;
   1739 	smu_data->power_tune_table.SviLoadLineVddC = defaults->SviLoadLineVddC;
   1740 	smu_data->power_tune_table.SviLoadLineTrimVddC = 3;
   1741 	smu_data->power_tune_table.SviLoadLineOffsetVddC = 0;
   1742 
   1743 	return 0;
   1744 }
   1745 
   1746 static int vegam_populate_tdc_limit(struct pp_hwmgr *hwmgr)
   1747 {
   1748 	uint16_t tdc_limit;
   1749 	struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend);
   1750 	struct phm_ppt_v1_information *table_info =
   1751 			(struct phm_ppt_v1_information *)(hwmgr->pptable);
   1752 	const struct vegam_pt_defaults *defaults = smu_data->power_tune_defaults;
   1753 
   1754 	tdc_limit = (uint16_t)(table_info->cac_dtp_table->usTDC * 128);
   1755 	smu_data->power_tune_table.TDC_VDDC_PkgLimit =
   1756 			CONVERT_FROM_HOST_TO_SMC_US(tdc_limit);
   1757 	smu_data->power_tune_table.TDC_VDDC_ThrottleReleaseLimitPerc =
   1758 			defaults->TDC_VDDC_ThrottleReleaseLimitPerc;
   1759 	smu_data->power_tune_table.TDC_MAWt = defaults->TDC_MAWt;
   1760 
   1761 	return 0;
   1762 }
   1763 
   1764 static int vegam_populate_dw8(struct pp_hwmgr *hwmgr, uint32_t fuse_table_offset)
   1765 {
   1766 	struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend);
   1767 	const struct vegam_pt_defaults *defaults = smu_data->power_tune_defaults;
   1768 	uint32_t temp;
   1769 
   1770 	if (smu7_read_smc_sram_dword(hwmgr,
   1771 			fuse_table_offset +
   1772 			offsetof(SMU75_Discrete_PmFuses, TdcWaterfallCtl),
   1773 			(uint32_t *)&temp, SMC_RAM_END))
   1774 		PP_ASSERT_WITH_CODE(false,
   1775 				"Attempt to read PmFuses.DW6 (SviLoadLineEn) from SMC Failed!",
   1776 				return -EINVAL);
   1777 	else {
   1778 		smu_data->power_tune_table.TdcWaterfallCtl = defaults->TdcWaterfallCtl;
   1779 		smu_data->power_tune_table.LPMLTemperatureMin =
   1780 				(uint8_t)((temp >> 16) & 0xff);
   1781 		smu_data->power_tune_table.LPMLTemperatureMax =
   1782 				(uint8_t)((temp >> 8) & 0xff);
   1783 		smu_data->power_tune_table.Reserved = (uint8_t)(temp & 0xff);
   1784 	}
   1785 	return 0;
   1786 }
   1787 
   1788 static int vegam_populate_temperature_scaler(struct pp_hwmgr *hwmgr)
   1789 {
   1790 	int i;
   1791 	struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend);
   1792 
   1793 	/* Currently not used. Set all to zero. */
   1794 	for (i = 0; i < 16; i++)
   1795 		smu_data->power_tune_table.LPMLTemperatureScaler[i] = 0;
   1796 
   1797 	return 0;
   1798 }
   1799 
   1800 static int vegam_populate_fuzzy_fan(struct pp_hwmgr *hwmgr)
   1801 {
   1802 	struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend);
   1803 
   1804 /* TO DO move to hwmgr */
   1805 	if ((hwmgr->thermal_controller.advanceFanControlParameters.usFanOutputSensitivity & (1 << 15))
   1806 		|| 0 == hwmgr->thermal_controller.advanceFanControlParameters.usFanOutputSensitivity)
   1807 		hwmgr->thermal_controller.advanceFanControlParameters.usFanOutputSensitivity =
   1808 			hwmgr->thermal_controller.advanceFanControlParameters.usDefaultFanOutputSensitivity;
   1809 
   1810 	smu_data->power_tune_table.FuzzyFan_PwmSetDelta = PP_HOST_TO_SMC_US(
   1811 				hwmgr->thermal_controller.advanceFanControlParameters.usFanOutputSensitivity);
   1812 	return 0;
   1813 }
   1814 
   1815 static int vegam_populate_gnb_lpml(struct pp_hwmgr *hwmgr)
   1816 {
   1817 	int i;
   1818 	struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend);
   1819 
   1820 	/* Currently not used. Set all to zero. */
   1821 	for (i = 0; i < 16; i++)
   1822 		smu_data->power_tune_table.GnbLPML[i] = 0;
   1823 
   1824 	return 0;
   1825 }
   1826 
   1827 static int vegam_populate_bapm_vddc_base_leakage_sidd(struct pp_hwmgr *hwmgr)
   1828 {
   1829 	struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend);
   1830 	struct phm_ppt_v1_information *table_info =
   1831 			(struct phm_ppt_v1_information *)(hwmgr->pptable);
   1832 	uint16_t hi_sidd = smu_data->power_tune_table.BapmVddCBaseLeakageHiSidd;
   1833 	uint16_t lo_sidd = smu_data->power_tune_table.BapmVddCBaseLeakageLoSidd;
   1834 	struct phm_cac_tdp_table *cac_table = table_info->cac_dtp_table;
   1835 
   1836 	hi_sidd = (uint16_t)(cac_table->usHighCACLeakage / 100 * 256);
   1837 	lo_sidd = (uint16_t)(cac_table->usLowCACLeakage / 100 * 256);
   1838 
   1839 	smu_data->power_tune_table.BapmVddCBaseLeakageHiSidd =
   1840 			CONVERT_FROM_HOST_TO_SMC_US(hi_sidd);
   1841 	smu_data->power_tune_table.BapmVddCBaseLeakageLoSidd =
   1842 			CONVERT_FROM_HOST_TO_SMC_US(lo_sidd);
   1843 
   1844 	return 0;
   1845 }
   1846 
   1847 static int vegam_populate_pm_fuses(struct pp_hwmgr *hwmgr)
   1848 {
   1849 	struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend);
   1850 	uint32_t pm_fuse_table_offset;
   1851 
   1852 	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
   1853 			PHM_PlatformCaps_PowerContainment)) {
   1854 		if (smu7_read_smc_sram_dword(hwmgr,
   1855 				SMU7_FIRMWARE_HEADER_LOCATION +
   1856 				offsetof(SMU75_Firmware_Header, PmFuseTable),
   1857 				&pm_fuse_table_offset, SMC_RAM_END))
   1858 			PP_ASSERT_WITH_CODE(false,
   1859 					"Attempt to get pm_fuse_table_offset Failed!",
   1860 					return -EINVAL);
   1861 
   1862 		if (vegam_populate_svi_load_line(hwmgr))
   1863 			PP_ASSERT_WITH_CODE(false,
   1864 					"Attempt to populate SviLoadLine Failed!",
   1865 					return -EINVAL);
   1866 
   1867 		if (vegam_populate_tdc_limit(hwmgr))
   1868 			PP_ASSERT_WITH_CODE(false,
   1869 					"Attempt to populate TDCLimit Failed!", return -EINVAL);
   1870 
   1871 		if (vegam_populate_dw8(hwmgr, pm_fuse_table_offset))
   1872 			PP_ASSERT_WITH_CODE(false,
   1873 					"Attempt to populate TdcWaterfallCtl, "
   1874 					"LPMLTemperature Min and Max Failed!",
   1875 					return -EINVAL);
   1876 
   1877 		if (0 != vegam_populate_temperature_scaler(hwmgr))
   1878 			PP_ASSERT_WITH_CODE(false,
   1879 					"Attempt to populate LPMLTemperatureScaler Failed!",
   1880 					return -EINVAL);
   1881 
   1882 		if (vegam_populate_fuzzy_fan(hwmgr))
   1883 			PP_ASSERT_WITH_CODE(false,
   1884 					"Attempt to populate Fuzzy Fan Control parameters Failed!",
   1885 					return -EINVAL);
   1886 
   1887 		if (vegam_populate_gnb_lpml(hwmgr))
   1888 			PP_ASSERT_WITH_CODE(false,
   1889 					"Attempt to populate GnbLPML Failed!",
   1890 					return -EINVAL);
   1891 
   1892 		if (vegam_populate_bapm_vddc_base_leakage_sidd(hwmgr))
   1893 			PP_ASSERT_WITH_CODE(false,
   1894 					"Attempt to populate BapmVddCBaseLeakage Hi and Lo "
   1895 					"Sidd Failed!", return -EINVAL);
   1896 
   1897 		if (smu7_copy_bytes_to_smc(hwmgr, pm_fuse_table_offset,
   1898 				(uint8_t *)&smu_data->power_tune_table,
   1899 				(sizeof(struct SMU75_Discrete_PmFuses) - PMFUSES_AVFSSIZE),
   1900 				SMC_RAM_END))
   1901 			PP_ASSERT_WITH_CODE(false,
   1902 					"Attempt to download PmFuseTable Failed!",
   1903 					return -EINVAL);
   1904 	}
   1905 	return 0;
   1906 }
   1907 
   1908 static int vegam_enable_reconfig_cus(struct pp_hwmgr *hwmgr)
   1909 {
   1910 	struct amdgpu_device *adev = hwmgr->adev;
   1911 
   1912 	smum_send_msg_to_smc_with_parameter(hwmgr,
   1913 					    PPSMC_MSG_EnableModeSwitchRLCNotification,
   1914 					    adev->gfx.cu_info.number);
   1915 
   1916 	return 0;
   1917 }
   1918 
   1919 static int vegam_init_smc_table(struct pp_hwmgr *hwmgr)
   1920 {
   1921 	int result;
   1922 	struct smu7_hwmgr *hw_data = (struct smu7_hwmgr *)(hwmgr->backend);
   1923 	struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend);
   1924 
   1925 	struct phm_ppt_v1_information *table_info =
   1926 			(struct phm_ppt_v1_information *)(hwmgr->pptable);
   1927 	struct SMU75_Discrete_DpmTable *table = &(smu_data->smc_state_table);
   1928 	uint8_t i;
   1929 	struct pp_atomctrl_gpio_pin_assignment gpio_pin;
   1930 	struct phm_ppt_v1_gpio_table *gpio_table =
   1931 			(struct phm_ppt_v1_gpio_table *)table_info->gpio_table;
   1932 	pp_atomctrl_clock_dividers_vi dividers;
   1933 
   1934 	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
   1935 			PHM_PlatformCaps_AutomaticDCTransition);
   1936 
   1937 	vegam_initialize_power_tune_defaults(hwmgr);
   1938 
   1939 	if (SMU7_VOLTAGE_CONTROL_NONE != hw_data->voltage_control)
   1940 		vegam_populate_smc_voltage_tables(hwmgr, table);
   1941 
   1942 	table->SystemFlags = 0;
   1943 	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
   1944 			PHM_PlatformCaps_AutomaticDCTransition))
   1945 		table->SystemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC;
   1946 
   1947 	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
   1948 			PHM_PlatformCaps_StepVddc))
   1949 		table->SystemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC;
   1950 
   1951 	if (hw_data->is_memory_gddr5)
   1952 		table->SystemFlags |= PPSMC_SYSTEMFLAG_GDDR5;
   1953 
   1954 	if (hw_data->ulv_supported && table_info->us_ulv_voltage_offset) {
   1955 		result = vegam_populate_ulv_state(hwmgr, table);
   1956 		PP_ASSERT_WITH_CODE(!result,
   1957 				"Failed to initialize ULV state!", return result);
   1958 		cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
   1959 				ixCG_ULV_PARAMETER, SMU7_CGULVPARAMETER_DFLT);
   1960 	}
   1961 
   1962 	result = vegam_populate_smc_link_level(hwmgr, table);
   1963 	PP_ASSERT_WITH_CODE(!result,
   1964 			"Failed to initialize Link Level!", return result);
   1965 
   1966 	result = vegam_populate_all_graphic_levels(hwmgr);
   1967 	PP_ASSERT_WITH_CODE(!result,
   1968 			"Failed to initialize Graphics Level!", return result);
   1969 
   1970 	result = vegam_populate_all_memory_levels(hwmgr);
   1971 	PP_ASSERT_WITH_CODE(!result,
   1972 			"Failed to initialize Memory Level!", return result);
   1973 
   1974 	result = vegam_populate_smc_acpi_level(hwmgr, table);
   1975 	PP_ASSERT_WITH_CODE(!result,
   1976 			"Failed to initialize ACPI Level!", return result);
   1977 
   1978 	result = vegam_populate_smc_vce_level(hwmgr, table);
   1979 	PP_ASSERT_WITH_CODE(!result,
   1980 			"Failed to initialize VCE Level!", return result);
   1981 
   1982 	/* Since only the initial state is completely set up at this point
   1983 	 * (the other states are just copies of the boot state) we only
   1984 	 * need to populate the  ARB settings for the initial state.
   1985 	 */
   1986 	result = vegam_program_memory_timing_parameters(hwmgr);
   1987 	PP_ASSERT_WITH_CODE(!result,
   1988 			"Failed to Write ARB settings for the initial state.", return result);
   1989 
   1990 	result = vegam_populate_smc_uvd_level(hwmgr, table);
   1991 	PP_ASSERT_WITH_CODE(!result,
   1992 			"Failed to initialize UVD Level!", return result);
   1993 
   1994 	result = vegam_populate_smc_boot_level(hwmgr, table);
   1995 	PP_ASSERT_WITH_CODE(!result,
   1996 			"Failed to initialize Boot Level!", return result);
   1997 
   1998 	result = vegam_populate_smc_initial_state(hwmgr);
   1999 	PP_ASSERT_WITH_CODE(!result,
   2000 			"Failed to initialize Boot State!", return result);
   2001 
   2002 	result = vegam_populate_bapm_parameters_in_dpm_table(hwmgr);
   2003 	PP_ASSERT_WITH_CODE(!result,
   2004 			"Failed to populate BAPM Parameters!", return result);
   2005 
   2006 	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
   2007 			PHM_PlatformCaps_ClockStretcher)) {
   2008 		result = vegam_populate_clock_stretcher_data_table(hwmgr);
   2009 		PP_ASSERT_WITH_CODE(!result,
   2010 				"Failed to populate Clock Stretcher Data Table!",
   2011 				return result);
   2012 	}
   2013 
   2014 	result = vegam_populate_avfs_parameters(hwmgr);
   2015 	PP_ASSERT_WITH_CODE(!result,
   2016 			"Failed to populate AVFS Parameters!", return result;);
   2017 
   2018 	table->CurrSclkPllRange = 0xff;
   2019 	table->GraphicsVoltageChangeEnable  = 1;
   2020 	table->GraphicsThermThrottleEnable  = 1;
   2021 	table->GraphicsInterval = 1;
   2022 	table->VoltageInterval  = 1;
   2023 	table->ThermalInterval  = 1;
   2024 	table->TemperatureLimitHigh =
   2025 			table_info->cac_dtp_table->usTargetOperatingTemp *
   2026 			SMU7_Q88_FORMAT_CONVERSION_UNIT;
   2027 	table->TemperatureLimitLow  =
   2028 			(table_info->cac_dtp_table->usTargetOperatingTemp - 1) *
   2029 			SMU7_Q88_FORMAT_CONVERSION_UNIT;
   2030 	table->MemoryVoltageChangeEnable = 1;
   2031 	table->MemoryInterval = 1;
   2032 	table->VoltageResponseTime = 0;
   2033 	table->PhaseResponseTime = 0;
   2034 	table->MemoryThermThrottleEnable = 1;
   2035 
   2036 	PP_ASSERT_WITH_CODE(hw_data->dpm_table.pcie_speed_table.count >= 1,
   2037 			"There must be 1 or more PCIE levels defined in PPTable.",
   2038 			return -EINVAL);
   2039 	table->PCIeBootLinkLevel =
   2040 			hw_data->dpm_table.pcie_speed_table.count;
   2041 	table->PCIeGenInterval = 1;
   2042 	table->VRConfig = 0;
   2043 
   2044 	result = vegam_populate_vr_config(hwmgr, table);
   2045 	PP_ASSERT_WITH_CODE(!result,
   2046 			"Failed to populate VRConfig setting!", return result);
   2047 
   2048 	table->ThermGpio = 17;
   2049 	table->SclkStepSize = 0x4000;
   2050 
   2051 	if (atomctrl_get_pp_assign_pin(hwmgr,
   2052 			VDDC_VRHOT_GPIO_PINID, &gpio_pin)) {
   2053 		table->VRHotGpio = gpio_pin.uc_gpio_pin_bit_shift;
   2054 		if (gpio_table)
   2055 			table->VRHotLevel =
   2056 					table_info->gpio_table->vrhot_triggered_sclk_dpm_index;
   2057 	} else {
   2058 		table->VRHotGpio = SMU7_UNUSED_GPIO_PIN;
   2059 		phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
   2060 				PHM_PlatformCaps_RegulatorHot);
   2061 	}
   2062 
   2063 	if (atomctrl_get_pp_assign_pin(hwmgr,
   2064 			PP_AC_DC_SWITCH_GPIO_PINID,	&gpio_pin)) {
   2065 		table->AcDcGpio = gpio_pin.uc_gpio_pin_bit_shift;
   2066 		if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
   2067 				PHM_PlatformCaps_AutomaticDCTransition) &&
   2068 				!smum_send_msg_to_smc(hwmgr, PPSMC_MSG_UseNewGPIOScheme))
   2069 			phm_cap_set(hwmgr->platform_descriptor.platformCaps,
   2070 					PHM_PlatformCaps_SMCtoPPLIBAcdcGpioScheme);
   2071 	} else {
   2072 		table->AcDcGpio = SMU7_UNUSED_GPIO_PIN;
   2073 		phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
   2074 				PHM_PlatformCaps_AutomaticDCTransition);
   2075 	}
   2076 
   2077 	/* Thermal Output GPIO */
   2078 	if (atomctrl_get_pp_assign_pin(hwmgr,
   2079 			THERMAL_INT_OUTPUT_GPIO_PINID, &gpio_pin)) {
   2080 		table->ThermOutGpio = gpio_pin.uc_gpio_pin_bit_shift;
   2081 
   2082 		/* For porlarity read GPIOPAD_A with assigned Gpio pin
   2083 		 * since VBIOS will program this register to set 'inactive state',
   2084 		 * driver can then determine 'active state' from this and
   2085 		 * program SMU with correct polarity
   2086 		 */
   2087 		table->ThermOutPolarity =
   2088 				(0 == (cgs_read_register(hwmgr->device, mmGPIOPAD_A) &
   2089 				(1 << gpio_pin.uc_gpio_pin_bit_shift))) ? 1:0;
   2090 		table->ThermOutMode = SMU7_THERM_OUT_MODE_THERM_ONLY;
   2091 
   2092 		/* if required, combine VRHot/PCC with thermal out GPIO */
   2093 		if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
   2094 				PHM_PlatformCaps_RegulatorHot) &&
   2095 			phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
   2096 				PHM_PlatformCaps_CombinePCCWithThermalSignal))
   2097 			table->ThermOutMode = SMU7_THERM_OUT_MODE_THERM_VRHOT;
   2098 	} else {
   2099 		table->ThermOutGpio = 17;
   2100 		table->ThermOutPolarity = 1;
   2101 		table->ThermOutMode = SMU7_THERM_OUT_MODE_DISABLE;
   2102 	}
   2103 
   2104 	/* Populate BIF_SCLK levels into SMC DPM table */
   2105 	for (i = 0; i <= hw_data->dpm_table.pcie_speed_table.count; i++) {
   2106 		result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
   2107 				smu_data->bif_sclk_table[i], &dividers);
   2108 		PP_ASSERT_WITH_CODE(!result,
   2109 				"Can not find DFS divide id for Sclk",
   2110 				return result);
   2111 
   2112 		if (i == 0)
   2113 			table->Ulv.BifSclkDfs =
   2114 					PP_HOST_TO_SMC_US((uint16_t)(dividers.pll_post_divider));
   2115 		else
   2116 			table->LinkLevel[i - 1].BifSclkDfs =
   2117 					PP_HOST_TO_SMC_US((uint16_t)(dividers.pll_post_divider));
   2118 	}
   2119 
   2120 	for (i = 0; i < SMU75_MAX_ENTRIES_SMIO; i++)
   2121 		table->Smio[i] = PP_HOST_TO_SMC_UL(table->Smio[i]);
   2122 
   2123 	CONVERT_FROM_HOST_TO_SMC_UL(table->SystemFlags);
   2124 	CONVERT_FROM_HOST_TO_SMC_UL(table->VRConfig);
   2125 	CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMask1);
   2126 	CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMask2);
   2127 	CONVERT_FROM_HOST_TO_SMC_UL(table->SclkStepSize);
   2128 	CONVERT_FROM_HOST_TO_SMC_UL(table->CurrSclkPllRange);
   2129 	CONVERT_FROM_HOST_TO_SMC_US(table->TemperatureLimitHigh);
   2130 	CONVERT_FROM_HOST_TO_SMC_US(table->TemperatureLimitLow);
   2131 	CONVERT_FROM_HOST_TO_SMC_US(table->VoltageResponseTime);
   2132 	CONVERT_FROM_HOST_TO_SMC_US(table->PhaseResponseTime);
   2133 
   2134 	/* Upload all dpm data to SMC memory.(dpm level, dpm level count etc) */
   2135 	result = smu7_copy_bytes_to_smc(hwmgr,
   2136 			smu_data->smu7_data.dpm_table_start +
   2137 			offsetof(SMU75_Discrete_DpmTable, SystemFlags),
   2138 			(uint8_t *)&(table->SystemFlags),
   2139 			sizeof(SMU75_Discrete_DpmTable) - 3 * sizeof(SMU75_PIDController),
   2140 			SMC_RAM_END);
   2141 	PP_ASSERT_WITH_CODE(!result,
   2142 			"Failed to upload dpm data to SMC memory!", return result);
   2143 
   2144 	result = vegam_populate_pm_fuses(hwmgr);
   2145 	PP_ASSERT_WITH_CODE(!result,
   2146 			"Failed to  populate PM fuses to SMC memory!", return result);
   2147 
   2148 	result = vegam_enable_reconfig_cus(hwmgr);
   2149 	PP_ASSERT_WITH_CODE(!result,
   2150 			"Failed to enable reconfigurable CUs!", return result);
   2151 
   2152 	return 0;
   2153 }
   2154 
   2155 static uint32_t vegam_get_offsetof(uint32_t type, uint32_t member)
   2156 {
   2157 	switch (type) {
   2158 	case SMU_SoftRegisters:
   2159 		switch (member) {
   2160 		case HandshakeDisables:
   2161 			return offsetof(SMU75_SoftRegisters, HandshakeDisables);
   2162 		case VoltageChangeTimeout:
   2163 			return offsetof(SMU75_SoftRegisters, VoltageChangeTimeout);
   2164 		case AverageGraphicsActivity:
   2165 			return offsetof(SMU75_SoftRegisters, AverageGraphicsActivity);
   2166 		case AverageMemoryActivity:
   2167 			return offsetof(SMU75_SoftRegisters, AverageMemoryActivity);
   2168 		case PreVBlankGap:
   2169 			return offsetof(SMU75_SoftRegisters, PreVBlankGap);
   2170 		case VBlankTimeout:
   2171 			return offsetof(SMU75_SoftRegisters, VBlankTimeout);
   2172 		case UcodeLoadStatus:
   2173 			return offsetof(SMU75_SoftRegisters, UcodeLoadStatus);
   2174 		case DRAM_LOG_ADDR_H:
   2175 			return offsetof(SMU75_SoftRegisters, DRAM_LOG_ADDR_H);
   2176 		case DRAM_LOG_ADDR_L:
   2177 			return offsetof(SMU75_SoftRegisters, DRAM_LOG_ADDR_L);
   2178 		case DRAM_LOG_PHY_ADDR_H:
   2179 			return offsetof(SMU75_SoftRegisters, DRAM_LOG_PHY_ADDR_H);
   2180 		case DRAM_LOG_PHY_ADDR_L:
   2181 			return offsetof(SMU75_SoftRegisters, DRAM_LOG_PHY_ADDR_L);
   2182 		case DRAM_LOG_BUFF_SIZE:
   2183 			return offsetof(SMU75_SoftRegisters, DRAM_LOG_BUFF_SIZE);
   2184 		}
   2185 		break;
   2186 	case SMU_Discrete_DpmTable:
   2187 		switch (member) {
   2188 		case UvdBootLevel:
   2189 			return offsetof(SMU75_Discrete_DpmTable, UvdBootLevel);
   2190 		case VceBootLevel:
   2191 			return offsetof(SMU75_Discrete_DpmTable, VceBootLevel);
   2192 		case LowSclkInterruptThreshold:
   2193 			return offsetof(SMU75_Discrete_DpmTable, LowSclkInterruptThreshold);
   2194 		}
   2195 		break;
   2196 	}
   2197 	pr_warn("can't get the offset of type %x member %x\n", type, member);
   2198 	return 0;
   2199 }
   2200 
   2201 static int vegam_program_mem_timing_parameters(struct pp_hwmgr *hwmgr)
   2202 {
   2203 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
   2204 
   2205 	if (data->need_update_smu7_dpm_table &
   2206 		(DPMTABLE_OD_UPDATE_SCLK +
   2207 		DPMTABLE_UPDATE_SCLK +
   2208 		DPMTABLE_UPDATE_MCLK))
   2209 		return vegam_program_memory_timing_parameters(hwmgr);
   2210 
   2211 	return 0;
   2212 }
   2213 
   2214 static int vegam_update_sclk_threshold(struct pp_hwmgr *hwmgr)
   2215 {
   2216 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
   2217 	struct vegam_smumgr *smu_data =
   2218 			(struct vegam_smumgr *)(hwmgr->smu_backend);
   2219 	int result = 0;
   2220 	uint32_t low_sclk_interrupt_threshold = 0;
   2221 
   2222 	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
   2223 			PHM_PlatformCaps_SclkThrottleLowNotification)
   2224 	    && (data->low_sclk_interrupt_threshold != 0)) {
   2225 		low_sclk_interrupt_threshold =
   2226 				data->low_sclk_interrupt_threshold;
   2227 
   2228 		CONVERT_FROM_HOST_TO_SMC_UL(low_sclk_interrupt_threshold);
   2229 
   2230 		result = smu7_copy_bytes_to_smc(
   2231 				hwmgr,
   2232 				smu_data->smu7_data.dpm_table_start +
   2233 				offsetof(SMU75_Discrete_DpmTable,
   2234 					LowSclkInterruptThreshold),
   2235 				(uint8_t *)&low_sclk_interrupt_threshold,
   2236 				sizeof(uint32_t),
   2237 				SMC_RAM_END);
   2238 	}
   2239 	PP_ASSERT_WITH_CODE((result == 0),
   2240 			"Failed to update SCLK threshold!", return result);
   2241 
   2242 	result = vegam_program_mem_timing_parameters(hwmgr);
   2243 	PP_ASSERT_WITH_CODE((result == 0),
   2244 			"Failed to program memory timing parameters!",
   2245 			);
   2246 
   2247 	return result;
   2248 }
   2249 
   2250 int vegam_thermal_avfs_enable(struct pp_hwmgr *hwmgr)
   2251 {
   2252 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
   2253 	int ret;
   2254 
   2255 	if (!hwmgr->avfs_supported)
   2256 		return 0;
   2257 
   2258 	ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_EnableAvfs);
   2259 	if (!ret) {
   2260 		if (data->apply_avfs_cks_off_voltage)
   2261 			ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_ApplyAvfsCksOffVoltage);
   2262 	}
   2263 
   2264 	return ret;
   2265 }
   2266 
   2267 static int vegam_thermal_setup_fan_table(struct pp_hwmgr *hwmgr)
   2268 {
   2269 	PP_ASSERT_WITH_CODE(hwmgr->thermal_controller.fanInfo.bNoFan,
   2270 			"VBIOS fan info is not correct!",
   2271 			);
   2272 	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
   2273 			PHM_PlatformCaps_MicrocodeFanControl);
   2274 	return 0;
   2275 }
   2276 
   2277 const struct pp_smumgr_func vegam_smu_funcs = {
   2278 	.name = "vegam_smu",
   2279 	.smu_init = vegam_smu_init,
   2280 	.smu_fini = smu7_smu_fini,
   2281 	.start_smu = vegam_start_smu,
   2282 	.check_fw_load_finish = smu7_check_fw_load_finish,
   2283 	.request_smu_load_fw = smu7_reload_firmware,
   2284 	.request_smu_load_specific_fw = NULL,
   2285 	.send_msg_to_smc = smu7_send_msg_to_smc,
   2286 	.send_msg_to_smc_with_parameter = smu7_send_msg_to_smc_with_parameter,
   2287 	.process_firmware_header = vegam_process_firmware_header,
   2288 	.is_dpm_running = vegam_is_dpm_running,
   2289 	.get_mac_definition = vegam_get_mac_definition,
   2290 	.update_smc_table = vegam_update_smc_table,
   2291 	.init_smc_table = vegam_init_smc_table,
   2292 	.get_offsetof = vegam_get_offsetof,
   2293 	.populate_all_graphic_levels = vegam_populate_all_graphic_levels,
   2294 	.populate_all_memory_levels = vegam_populate_all_memory_levels,
   2295 	.update_sclk_threshold = vegam_update_sclk_threshold,
   2296 	.is_hw_avfs_present = vegam_is_hw_avfs_present,
   2297 	.thermal_avfs_enable = vegam_thermal_avfs_enable,
   2298 	.thermal_setup_fan_table = vegam_thermal_setup_fan_table,
   2299 };
   2300