HomeSort by: relevance | last modified time | path
    Searched refs:vgpu_vreg (Results 1 - 9 of 9) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/i915/gvt/
edid.c 146 memcpy(&vgpu_vreg(vgpu, offset), p_data, bytes);
148 pin_select = vgpu_vreg(vgpu, offset) & _GMBUS_PIN_SEL_MASK;
187 if (vgpu_vreg(vgpu, offset) & GMBUS_SW_CLR_INT) {
189 vgpu_vreg(vgpu, offset) &= ~GMBUS_SW_CLR_INT;
242 if (gmbus1_bus_cycle(vgpu_vreg(vgpu, offset))
276 vgpu_vreg(vgpu, offset) = wvalue;
302 memcpy(p_data, &vgpu_vreg(vgpu, offset), bytes);
313 memcpy(&vgpu_vreg(vgpu, offset), &reg_data, byte_count);
314 memcpy(p_data, &vgpu_vreg(vgpu, offset), bytes);
335 memcpy(p_data, &vgpu_vreg(vgpu, offset), bytes)
    [all...]
interrupt.c 187 trace_write_ir(vgpu->id, "IMR", reg, imr, vgpu_vreg(vgpu, reg),
188 (vgpu_vreg(vgpu, reg) ^ imr));
190 vgpu_vreg(vgpu, reg) = imr;
216 u32 virtual_ier = vgpu_vreg(vgpu, reg);
228 vgpu_vreg(vgpu, reg) &= ~GEN8_MASTER_IRQ_CONTROL;
229 vgpu_vreg(vgpu, reg) |= ier;
257 trace_write_ir(vgpu->id, "IER", reg, ier, vgpu_vreg(vgpu, reg),
258 (vgpu_vreg(vgpu, reg) ^ ier));
260 vgpu_vreg(vgpu, reg) = ier;
294 trace_write_ir(vgpu->id, "IIR", reg, iir, vgpu_vreg(vgpu, reg)
    [all...]
handlers.c 80 memcpy(p_data, &vgpu_vreg(vgpu, offset), bytes);
86 memcpy(&vgpu_vreg(vgpu, offset), p_data, bytes);
288 old = vgpu_vreg(vgpu, offset);
311 vgpu_vreg(vgpu, offset) = new;
312 vgpu_vreg(vgpu, ack_reg_offset) = (new & GENMASK(15, 0));
323 data = vgpu_vreg(vgpu, offset);
360 vgpu_vreg(vgpu, offset) = 0;
382 if (vgpu_vreg(vgpu, offset) & PANEL_POWER_ON) {
400 if (vgpu_vreg(vgpu, offset) & TRANS_ENABLE)
401 vgpu_vreg(vgpu, offset) |= TRANS_STATE_ENABLE
    [all...]
execlist.c 105 status.ldw = vgpu_vreg(vgpu, status_reg);
106 status.udw = vgpu_vreg(vgpu, status_reg + 4);
124 vgpu_vreg(vgpu, status_reg) = status.ldw;
125 vgpu_vreg(vgpu, status_reg + 4) = status.udw;
148 ctx_status_ptr.dw = vgpu_vreg(vgpu, ctx_status_ptr_reg);
161 vgpu_vreg(vgpu, offset) = status->ldw;
162 vgpu_vreg(vgpu, offset + 4) = status->udw;
165 vgpu_vreg(vgpu, ctx_status_ptr_reg) = ctx_status_ptr.dw;
274 status.ldw = vgpu_vreg(vgpu, status_reg);
275 status.udw = vgpu_vreg(vgpu, status_reg + 4)
    [all...]
debugfs.c 72 vreg = vgpu_vreg(param->vgpu, offset);
display.c 45 u32 data = vgpu_vreg(vgpu, _TRANS_DDI_FUNC_CTL_EDP);
70 if (!(vgpu_vreg(vgpu, _TRANS_DDI_FUNC_CTL_EDP) & TRANS_DDI_FUNC_ENABLE))
scheduler.c 225 vgpu_vreg(vgpu, i915_mmio_reg_offset(reg)) = I915_READ_FW(reg);
227 vgpu_vreg(vgpu, i915_mmio_reg_offset(reg)) = I915_READ_FW(reg);
229 vgpu_vreg(vgpu, i915_mmio_reg_offset(reg)) = I915_READ_FW(reg);
gvt.h 449 #define vgpu_vreg(vgpu, offset) \ macro
cmd_parser.c 882 vgpu_vreg(s->vgpu, offset) = cmd_val(s, index + 1);
947 vgpu_vreg(vgpu, offset) = data;

Completed in 19 milliseconds