HomeSort by: relevance | last modified time | path
    Searched refs:viewport_width (Results 1 - 15 of 15) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/calcs/
amdgpu_dcn_calcs.c 338 input->src.viewport_width = pipe->plane_res.scl_data.viewport.width;
366 input->src.viewport_width_c = input->src.viewport_width / 2;
372 input->src.viewport_width_c = input->src.viewport_width / 2;
379 input->src.viewport_width_c = input->src.viewport_width;
384 input->src.viewport_width_c = input->src.viewport_width;
894 v->viewport_width[input_idx] = pipe->stream->timing.h_addressable;
903 if (v->viewport_width[input_idx] > 1920)
904 v->viewport_width[input_idx] = 1920;
907 v->scaler_rec_out_width[input_idx] = v->viewport_width[input_idx];
917 v->viewport_width[input_idx] = pipe->plane_res.scl_data.viewport.width
    [all...]
amdgpu_dcn_calc_auto.c 51 v->h_ratio[k] = v->viewport_width[k] / v->scaler_rec_out_width[k];
56 v->v_ratio[k] = v->viewport_width[k] / v->scaler_recout_height[k];
61 v->h_ratio[k] =dcn_bw_max2(v->viewport_width[k] / v->scaler_rec_out_width[k], v->viewport_height[k] / v->scaler_recout_height[k]);
64 v->h_ratio[k] =dcn_bw_max2(v->viewport_height[k] / v->scaler_rec_out_width[k], v->viewport_width[k] / v->scaler_recout_height[k]);
153 v->swath_width_ysingle_dpp[k] = v->viewport_width[k];
626 v->meta_surface_width_y =dcn_bw_ceil2(v->viewport_width[k] / v->no_of_dpp[i][j][k] - 1.0, v->meta_req_width_y) + v->meta_req_width_y;
670 v->dpte_bytes_per_row_y = 64.0 * (dcn_bw_ceil2((v->viewport_width[k] / v->no_of_dpp[i][j][k] *dcn_bw_min2(128.0, dcn_bw_pow(2.0,dcn_bw_floor2(dcn_bw_log(v->pte_buffer_size_in_requests * v->data_pte_req_width_y / (v->viewport_width[k] / v->no_of_dpp[i][j][k]), 2.0), 1.0))) - 1.0) / v->data_pte_req_width_y, 1.0) + 1);
673 v->dpte_bytes_per_row_y = 64.0 * (dcn_bw_ceil2((v->viewport_width[k] / v->no_of_dpp[i][j][k] - 1.0) / v->data_pte_req_width_y, 1.0) + 1);
686 v->meta_surface_width_c =dcn_bw_ceil2(v->viewport_width[k] / v->no_of_dpp[i][j][k] / 2.0 - 1.0, v->meta_req_width_c) + v->meta_req_width_c
    [all...]
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dml/
display_mode_structs.h 236 unsigned int viewport_width; member in struct:_vcs_dpi_display_pipe_source_params_st
amdgpu_display_mode_vba.c 392 src->viewport_width;
405 mode_lib->vba.SurfaceWidthY[mode_lib->vba.NumberOfActivePlanes] = src->viewport_width;
607 src_k->viewport_width;
609 src_k->viewport_width;
amdgpu_dml1_display_rq_dlg_calc.c 617 vp_width = pipe_src_param.viewport_width / ppe;
1199 vp_width_l = e2e_pipe_param.pipe.src.viewport_width;
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn10/
amdgpu_dcn10_hw_sequencer_debug.c 152 s->viewport_width,
172 s->viewport_width,
amdgpu_dcn10_hw_sequencer.c 178 s->viewport_width,
3021 int viewport_width = local in function:dcn10_set_cursor_position
3027 if (pos_cpy.x >= viewport_width + viewport_x) {
3028 pos_cpy.x = 2 * viewport_width
3038 pos_cpy.x = temp_x + viewport_width;
3042 pos_cpy.x = viewport_width - pos_cpy.x + 2 * viewport_x;
dcn10_hubp.h 668 uint32_t viewport_width; member in struct:dcn_hubp_state
amdgpu_dcn10_hubp.c 1002 PRI_VIEWPORT_WIDTH, &s->viewport_width,
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/inc/
dcn_calcs.h 177 float viewport_width[number_of_planes_minus_one + 1]; member in struct:dcn_bw_internal_vars
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn20/
amdgpu_dcn20_resource.c 2073 pipes[pipe_cnt].pipe.src.viewport_width = timing->h_addressable;
2074 if (pipes[pipe_cnt].pipe.src.viewport_width > 1920)
2075 pipes[pipe_cnt].pipe.src.viewport_width = 1920;
2080 pipes[pipe_cnt].pipe.src.surface_width_y = pipes[pipe_cnt].pipe.src.viewport_width;
2082 pipes[pipe_cnt].pipe.src.surface_width_c = pipes[pipe_cnt].pipe.src.viewport_width;
2083 pipes[pipe_cnt].pipe.src.data_pitch = ((pipes[pipe_cnt].pipe.src.viewport_width + 63) / 64) * 64; /* linear sw only */
2085 pipes[pipe_cnt].pipe.dest.recout_width = pipes[pipe_cnt].pipe.src.viewport_width; /*vp_width/hratio*/
2112 pipes[pipe_cnt].pipe.src.viewport_width = scl->viewport.width;
amdgpu_dcn20_hubp.c 1194 PRI_VIEWPORT_WIDTH, &s->viewport_width,
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dml/dcn20/
amdgpu_display_rq_dlg_calc_20.c 692 vp_width = pipe_src_param.viewport_width / ppe;
971 vp_width_l = src->viewport_width;
amdgpu_display_rq_dlg_calc_20v2.c 692 vp_width = pipe_src_param.viewport_width / ppe;
972 vp_width_l = src->viewport_width;
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dml/dcn21/
amdgpu_display_rq_dlg_calc_21.c 701 vp_width = pipe_param.src.viewport_width / ppe;
1023 vp_width_l = src->viewport_width;

Completed in 30 milliseconds