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    Searched refs:vlv (Results 1 - 5 of 5) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/i915/
intel_pm.c 422 * Note that on VLV/CHV this actually only controls the max FIFO mode,
447 dev_priv->wm.vlv.cxsr = enable;
478 struct vlv_fifo_state *fifo_state = &crtc_state->wm.vlv.fifo_state;
1679 &crtc_state->wm.vlv.raw[VLV_WM_LEVEL_PM2];
1680 struct vlv_fifo_state *fifo_state = &crtc_state->wm.vlv.fifo_state;
1794 struct g4x_pipe_wm *raw = &crtc_state->wm.vlv.raw[level];
1819 struct g4x_pipe_wm *raw = &crtc_state->wm.vlv.raw[level];
1838 crtc_state->wm.vlv.raw[VLV_WM_LEVEL_PM2].plane[plane_id],
1839 crtc_state->wm.vlv.raw[VLV_WM_LEVEL_PM5].plane[plane_id],
1840 crtc_state->wm.vlv.raw[VLV_WM_LEVEL_DDR_DVFS].plane[plane_id])
    [all...]
i915_drv.h 854 /* TV/DP on pre-gen5/vlv can't use the pipe source. */
1218 struct vlv_wm_values vlv; member in union:drm_i915_private::__anon6c72b20e1108::__anon6c72b20e120a
  /src/sys/external/bsd/drm2/dist/drm/i915/display/
intel_display_power.h 169 } vlv; member in union:i915_power_well_desc::__anon93be6b3d010a
intel_display_power.c 1152 int pw_idx = power_well->desc->vlv.idx;
1200 int pw_idx = power_well->desc->vlv.idx;
1355 * 6. De-assert cmn_reset/side_reset. Same as VLV X0.
2902 .vlv.idx = PUNIT_PWGT_IDX_DISP2D,
2914 .vlv.idx = PUNIT_PWGT_IDX_DPIO_TX_B_LANES_01,
2926 .vlv.idx = PUNIT_PWGT_IDX_DPIO_TX_B_LANES_23,
2938 .vlv.idx = PUNIT_PWGT_IDX_DPIO_TX_C_LANES_01,
2950 .vlv.idx = PUNIT_PWGT_IDX_DPIO_TX_C_LANES_23,
2959 .vlv.idx = PUNIT_PWGT_IDX_DPIO_CMN_BC,
2989 .vlv.idx = PUNIT_PWGT_IDX_DPIO_CMN_BC
    [all...]
intel_display_types.h 754 } vlv; member in union:intel_crtc_wm_state::__anonde7c4d45070a
954 /* Panel fitter controls for gen2-gen4 + VLV */
1089 struct vlv_wm_state vlv; member in union:intel_crtc::__anonde7c4d451308::__anonde7c4d45140a
1274 * this port. Only relevant on VLV/CHV.
1280 * external DP as that will mess things up on VLV.

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