HomeSort by: relevance | last modified time | path
    Searched refs:vlv_punit_read (Results 1 - 8 of 8) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/i915/
intel_sideband.h 122 u32 vlv_punit_read(struct drm_i915_private *i915, u32 addr);
intel_sideband.c 147 u32 vlv_punit_read(struct drm_i915_private *i915, u32 addr) function in typeref:typename:u32
intel_pm.c 315 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
324 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
338 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM);
6066 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM);
6079 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
6083 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
6090 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
i915_debugfs.c 822 freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
  /src/sys/external/bsd/drm2/dist/drm/i915/gt/
intel_rps.c 952 val = vlv_punit_read(i915, FB_GFX_FMAX_AT_VMAX_FUSE);
979 val = vlv_punit_read(i915, PUNIT_GPU_DUTYCYCLE_REG);
990 val = vlv_punit_read(i915, FB_GFX_FMAX_AT_VMAX_FUSE);
1000 val = vlv_punit_read(i915, FB_GFX_FMIN_AT_VMIN_FUSE);
1035 val = vlv_punit_read(i915, PUNIT_REG_GPU_FREQ_STS);
1093 val = vlv_punit_read(i915, PUNIT_REG_GPU_LFM) & 0xff;
1132 val = vlv_punit_read(i915, PUNIT_REG_GPU_FREQ_STS);
1312 val = vlv_punit_read(i915, PUNIT_REG_GPU_FREQ_STS);
1711 freq = vlv_punit_read(i915, PUNIT_REG_GPU_FREQ_STS);
debugfs_gt_pm.c 279 freq_sts = vlv_punit_read(i915, PUNIT_REG_GPU_FREQ_STS);
  /src/sys/external/bsd/drm2/dist/drm/i915/display/
intel_cdclk.c 482 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM);
564 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM);
568 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM) &
646 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM);
650 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM) &
intel_display_power.c 1164 ((vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask) == state)
1169 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL);
1177 vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL));
1211 state = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask;
1225 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL) & mask;
1714 state = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM) & DP_SSS_MASK(pipe);
1726 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM) & DP_SSC_MASK(pipe);
1747 ((vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM) & DP_SSS_MASK(pipe)) == state)
1752 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM);
1760 vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM))
    [all...]

Completed in 29 milliseconds