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    Searched refs:vmw_write (Results 1 - 8 of 8) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/vmwgfx/
vmwgfx_ldu.c 121 vmw_write(dev_priv, SVGA_REG_NUM_GUEST_DISPLAYS,
128 vmw_write(dev_priv, SVGA_REG_DISPLAY_ID, i);
129 vmw_write(dev_priv, SVGA_REG_DISPLAY_IS_PRIMARY, !i);
130 vmw_write(dev_priv, SVGA_REG_DISPLAY_POSITION_X, crtc->x);
131 vmw_write(dev_priv, SVGA_REG_DISPLAY_POSITION_Y, crtc->y);
132 vmw_write(dev_priv, SVGA_REG_DISPLAY_WIDTH, crtc->mode.hdisplay);
133 vmw_write(dev_priv, SVGA_REG_DISPLAY_HEIGHT, crtc->mode.vdisplay);
134 vmw_write(dev_priv, SVGA_REG_DISPLAY_ID, SVGA_ID_INVALID);
vmwgfx_fifo.c 62 vmw_write(dev_priv, SVGA_REG_DEV_CAP, SVGA3D_DEVCAP_3D);
137 vmw_write(dev_priv, SVGA_REG_ENABLE, SVGA_REG_ENABLE_ENABLE |
139 vmw_write(dev_priv, SVGA_REG_TRACES, 0);
157 vmw_write(dev_priv, SVGA_REG_CONFIG_DONE, 1);
181 vmw_write(dev_priv, SVGA_REG_SYNC, reason);
189 vmw_write(dev_priv, SVGA_REG_SYNC, SVGA_SYNC_GENERIC);
195 vmw_write(dev_priv, SVGA_REG_CONFIG_DONE,
197 vmw_write(dev_priv, SVGA_REG_ENABLE,
199 vmw_write(dev_priv, SVGA_REG_TRACES,
vmwgfx_kms.c 1888 vmw_write(vmw_priv, SVGA_REG_PITCHLOCK, pitch);
1892 vmw_write(vmw_priv, SVGA_REG_WIDTH, width);
1893 vmw_write(vmw_priv, SVGA_REG_HEIGHT, height);
1894 vmw_write(vmw_priv, SVGA_REG_BITS_PER_PIXEL, bpp);
1931 vmw_write(vmw_priv, SVGA_REG_DISPLAY_ID, i);
1937 vmw_write(vmw_priv, SVGA_REG_DISPLAY_ID, SVGA_ID_INVALID);
1959 vmw_write(vmw_priv, SVGA_REG_WIDTH, vmw_priv->vga_width);
1960 vmw_write(vmw_priv, SVGA_REG_HEIGHT, vmw_priv->vga_height);
1961 vmw_write(vmw_priv, SVGA_REG_BITS_PER_PIXEL, vmw_priv->vga_bpp);
1963 vmw_write(vmw_priv, SVGA_REG_PITCHLOCK
    [all...]
vmwgfx_drv.c 687 vmw_write(dev_priv, SVGA_REG_ID, SVGA_ID_2);
755 vmw_write(dev_priv, SVGA_REG_DEV_CAP,
759 vmw_write(dev_priv, SVGA_REG_DEV_CAP,
935 vmw_write(dev_priv, SVGA_REG_DEV_CAP, SVGA3D_DEVCAP_DXCONTEXT);
956 vmw_write(dev_priv, SVGA_REG_DEV_CAP,
1235 vmw_write(dev_priv, SVGA_REG_ENABLE, SVGA_REG_ENABLE);
1265 vmw_write(dev_priv, SVGA_REG_ENABLE,
1301 vmw_write(dev_priv, SVGA_REG_ENABLE,
1451 vmw_write(dev_priv, SVGA_REG_ID, SVGA_ID_2);
vmwgfx_irq.c 339 vmw_write(dev_priv, SVGA_REG_IRQMASK, dev_priv->irq_mask);
350 vmw_write(dev_priv, SVGA_REG_IRQMASK, dev_priv->irq_mask);
461 vmw_write(dev_priv, SVGA_REG_IRQMASK, 0);
vmwgfx_ioctl.c 170 vmw_write(dev_priv, SVGA_REG_DEV_CAP, i);
227 vmw_write(dev_priv, SVGA_REG_DEV_CAP, i);
vmwgfx_cmdbuf.c 318 vmw_write(man->dev_priv, SVGA_REG_COMMAND_HIGH, val);
322 vmw_write(man->dev_priv, SVGA_REG_COMMAND_LOW, val);
vmwgfx_drv.h 668 static inline void vmw_write(struct vmw_private *dev_priv, function

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