| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn10/ |
| amdgpu_dcn10_optc.c | 67 int vready_offset,
74 optc1->vready_offset = vready_offset;
92 VREADY_OFFSET, optc1->vready_offset);
147 int vready_offset,
167 optc1->vready_offset = vready_offset;
275 vready_offset,
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| dcn10_optc.h | 181 SF(OTG0_OTG_VREADY_PARAM, VREADY_OFFSET, mask_sh),\
319 type VREADY_OFFSET;\
513 int vready_offset; member in struct:optc
554 int vready_offset,
574 int vready_offset,
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| amdgpu_dcn10_hubp.c | 136 if ((pipe_dest->vstartup_start - 2*(pipe_dest->vready_offset+pipe_dest->vupdate_width
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| amdgpu_dcn10_hw_sequencer.c | 811 pipe_ctx->pipe_dlg_param.vready_offset,
2465 pipe_ctx->pipe_dlg_param.vready_offset,
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| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/inc/hw/ |
| timing_generator.h | 143 int vready_offset,
223 int vready_offset,
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| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce110/ |
| dce110_timing_generator.h | 262 int vready_offset,
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| amdgpu_dce110_timing_generator_v.c | 443 int vready_offset,
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| amdgpu_dce110_timing_generator.c | 1965 int vready_offset,
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| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce80/ |
| amdgpu_dce80_timing_generator.c | 115 int vready_offset,
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| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dml/ |
| display_mode_structs.h | 328 unsigned int vready_offset; member in struct:_vcs_dpi_display_pipe_dest_params_st
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| amdgpu_dml1_display_rq_dlg_calc.c | 1050 unsigned int vready_offset; local in function:dml1_rq_dlg_get_dlg_params
1232 vready_offset = e2e_pipe_param.pipe.dest.vready_offset;
1301 line_setup = (double) (vupdate_offset + vupdate_width + vready_offset) / (double) htotal;
1328 DTRACE("DLG: %s: vready_offset = %d", __func__, vready_offset);
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| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dml/dcn20/ |
| amdgpu_display_rq_dlg_calc_20.c | 853 unsigned int vready_offset; local in function:dml20_rq_dlg_get_dlg_params
1006 vready_offset = dst->vready_offset;
1031 - (double) (vready_offset + vupdate_width + vupdate_offset) / htotal
1038 - (double) (vready_offset + vupdate_width + vupdate_offset) / htotal
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| amdgpu_display_rq_dlg_calc_20v2.c | 853 unsigned int vready_offset; local in function:dml20v2_rq_dlg_get_dlg_params
1007 vready_offset = dst->vready_offset;
1032 - (double) (vready_offset + vupdate_width + vupdate_offset) / htotal
1039 - (double) (vready_offset + vupdate_width + vupdate_offset) / htotal
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| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dml/dcn21/ |
| amdgpu_display_rq_dlg_calc_21.c | 899 unsigned int vready_offset; local in function:dml_rq_dlg_get_dlg_params
1046 vready_offset = dst->vready_offset;
1071 - (double) (vready_offset + vupdate_width + vupdate_offset) / htotal
1078 - (double) (vready_offset + vupdate_width + vupdate_offset) / htotal
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| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn20/ |
| amdgpu_dcn20_hwseq.c | 656 pipe_ctx->pipe_dlg_param.vready_offset,
1214 if (old_pipe->pipe_dlg_param.vready_offset != new_pipe->pipe_dlg_param.vready_offset
1486 pipe_ctx->pipe_dlg_param.vready_offset,
1726 pipe_ctx->pipe_dlg_param.vready_offset,
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| amdgpu_dcn20_hubp.c | 183 if (VSTARTUP_START - (VREADY_OFFSET+VUPDATE_WIDTH+VUPDATE_OFFSET)/htotal)
189 if ((pipe_dest->vstartup_start - (pipe_dest->vready_offset+pipe_dest->vupdate_width
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| amdgpu_dcn20_resource.c | 2814 dst->vready_offset = context->bw_ctx.dml.vba.VReadyOffsetPix[pipe_idx_unsplit];
2829 dst_j->vready_offset = context->bw_ctx.dml.vba.VReadyOffsetPix[pipe_idx_unsplit];
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| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce120/ |
| amdgpu_dce120_timing_generator.c | 744 int vready_offset,
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| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/calcs/ |
| amdgpu_dcn_calcs.c | 1185 pipe->pipe_dlg_param.vready_offset = v->v_ready_offset_pix[input_idx];
1226 hsplit_pipe->pipe_dlg_param.vready_offset = v->v_ready_offset_pix[input_idx];
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