| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn10/ |
| amdgpu_dcn10_optc.c | 69 int vupdate_offset,
76 optc1->vupdate_offset = vupdate_offset;
88 VUPDATE_OFFSET, optc1->vupdate_offset,
149 int vupdate_offset,
169 optc1->vupdate_offset = vupdate_offset;
277 vupdate_offset,
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| dcn10_optc.h | 179 SF(OTG0_OTG_VUPDATE_PARAM, VUPDATE_OFFSET, mask_sh),\
317 type VUPDATE_OFFSET;\
511 int vupdate_offset; member in struct:optc
556 int vupdate_offset,
576 int vupdate_offset,
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| amdgpu_dcn10_hubp.c | 137 + pipe_dest->vupdate_offset) / pipe_dest->htotal) <= pipe_dest->vblank_end) {
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| amdgpu_dcn10_hw_sequencer.c | 813 pipe_ctx->pipe_dlg_param.vupdate_offset,
2467 pipe_ctx->pipe_dlg_param.vupdate_offset,
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| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/inc/hw/ |
| timing_generator.h | 145 int vupdate_offset,
225 int vupdate_offset,
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| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce110/ |
| dce110_timing_generator.h | 264 int vupdate_offset,
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| amdgpu_dce110_timing_generator_v.c | 445 int vupdate_offset,
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| amdgpu_dce110_timing_generator.c | 1967 int vupdate_offset,
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| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce80/ |
| amdgpu_dce80_timing_generator.c | 117 int vupdate_offset,
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| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dml/ |
| display_mode_structs.h | 326 unsigned int vupdate_offset; member in struct:_vcs_dpi_display_pipe_dest_params_st
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| amdgpu_dml1_display_rq_dlg_calc.c | 1048 unsigned int vupdate_offset; local in function:dml1_rq_dlg_get_dlg_params
1230 vupdate_offset = e2e_pipe_param.pipe.dest.vupdate_offset;
1301 line_setup = (double) (vupdate_offset + vupdate_width + vready_offset) / (double) htotal;
1326 DTRACE("DLG: %s: vupdate_offset = %d", __func__, vupdate_offset);
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| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dml/dcn20/ |
| amdgpu_display_rq_dlg_calc_20.c | 851 unsigned int vupdate_offset; local in function:dml20_rq_dlg_get_dlg_params
1004 vupdate_offset = dst->vupdate_offset;
1031 - (double) (vready_offset + vupdate_width + vupdate_offset) / htotal
1038 - (double) (vready_offset + vupdate_width + vupdate_offset) / htotal
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| amdgpu_display_rq_dlg_calc_20v2.c | 851 unsigned int vupdate_offset; local in function:dml20v2_rq_dlg_get_dlg_params
1005 vupdate_offset = dst->vupdate_offset;
1032 - (double) (vready_offset + vupdate_width + vupdate_offset) / htotal
1039 - (double) (vready_offset + vupdate_width + vupdate_offset) / htotal
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| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dml/dcn21/ |
| amdgpu_display_rq_dlg_calc_21.c | 897 unsigned int vupdate_offset; local in function:dml_rq_dlg_get_dlg_params
1044 vupdate_offset = dst->vupdate_offset;
1071 - (double) (vready_offset + vupdate_width + vupdate_offset) / htotal
1078 - (double) (vready_offset + vupdate_width + vupdate_offset) / htotal
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| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/calcs/ |
| amdgpu_dcn_calcs.c | 437 input->dest.vupdate_offset = pipe->pipe_dlg_param.vupdate_offset;
438 input->dest.vupdate_offset = pipe->pipe_dlg_param.vupdate_offset;
1184 pipe->pipe_dlg_param.vupdate_offset = v->v_update_offset_pix[input_idx];
1225 hsplit_pipe->pipe_dlg_param.vupdate_offset = v->v_update_offset_pix[input_idx];
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| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn20/ |
| amdgpu_dcn20_hwseq.c | 658 pipe_ctx->pipe_dlg_param.vupdate_offset,
1216 || old_pipe->pipe_dlg_param.vupdate_offset != new_pipe->pipe_dlg_param.vupdate_offset
1488 pipe_ctx->pipe_dlg_param.vupdate_offset,
1728 pipe_ctx->pipe_dlg_param.vupdate_offset,
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| amdgpu_dcn20_hubp.c | 183 if (VSTARTUP_START - (VREADY_OFFSET+VUPDATE_WIDTH+VUPDATE_OFFSET)/htotal)
190 + pipe_dest->vupdate_offset) / pipe_dest->htotal) <= pipe_dest->vblank_end) {
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| amdgpu_dcn20_resource.c | 2812 dst->vupdate_offset = context->bw_ctx.dml.vba.VUpdateOffsetPix[pipe_idx_unsplit];
2827 dst_j->vupdate_offset = context->bw_ctx.dml.vba.VUpdateOffsetPix[pipe_idx_unsplit];
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| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce120/ |
| amdgpu_dce120_timing_generator.c | 746 int vupdate_offset,
|
