| /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/ |
| amdgpu_ih.c | 114 unsigned wptr_offs, rptr_offs; local in function:amdgpu_ih_ring_init
116 r = amdgpu_device_wb_get(adev, &wptr_offs);
122 amdgpu_device_wb_free(adev, wptr_offs);
132 amdgpu_device_wb_free(adev, wptr_offs);
136 ih->wptr_addr = adev->wb.gpu_addr + wptr_offs * 4;
137 ih->wptr_cpu = &adev->wb.wb[wptr_offs];
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| amdgpu_jpeg_v2_5.c | 413 return adev->wb.wb[ring->wptr_offs];
430 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr);
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| amdgpu_ring.c | 280 r = amdgpu_device_wb_get(adev, &ring->wptr_offs);
282 dev_err(adev->dev, "(%d) ring wptr_offs wb alloc failed\n", r);
368 amdgpu_device_wb_free(ring->adev, ring->wptr_offs);
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| amdgpu_vcn_v2_0.c | 1263 return adev->wb.wb[ring->wptr_offs];
1284 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr);
1487 return adev->wb.wb[ring->wptr_offs];
1492 return adev->wb.wb[ring->wptr_offs];
1511 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr);
1518 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr);
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| amdgpu_vcn_v2_5.c | 1456 return adev->wb.wb[ring->wptr_offs];
1477 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr);
1544 return adev->wb.wb[ring->wptr_offs];
1549 return adev->wb.wb[ring->wptr_offs];
1568 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr);
1575 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr);
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| amdgpu_jpeg_v2_0.c | 434 return adev->wb.wb[ring->wptr_offs];
451 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr);
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| amdgpu_vce_v4_0.c | 92 return adev->wb.wb[ring->wptr_offs];
115 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr);
186 adev->wb.wb[adev->vce.ring[0].wptr_offs] = 0;
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| amdgpu_sdma_v5_0.c | 301 wptr = ((volatile u64 *)&adev->wb.wb[ring->wptr_offs]);
336 "wptr_offs == 0x%08x "
339 ring->wptr_offs,
343 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr << 2);
344 adev->wb.wb[ring->wptr_offs + 1] = upper_32_bits(ring->wptr << 2);
653 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
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| amdgpu_sdma_v4_0.c | 673 wptr = READ_ONCE(*((volatile u64 *)&adev->wb.wb[ring->wptr_offs]));
699 volatile u64 *wb = (volatile u64 *)&adev->wb.wb[ring->wptr_offs];
702 "wptr_offs == 0x%08x "
705 ring->wptr_offs,
742 wptr = READ_ONCE(*((volatile u64 *)&adev->wb.wb[ring->wptr_offs]));
764 volatile u64 *wb = (volatile u64 *)&adev->wb.wb[ring->wptr_offs];
1145 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
1236 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
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| amdgpu_ring.h | 210 unsigned wptr_offs; member in struct:amdgpu_ring
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| amdgpu_sdma_v3_0.c | 376 wptr = ring->adev->wb.wb[ring->wptr_offs] >> 2;
396 volatile u32 *wb = (volatile u32 *)&adev->wb.wb[ring->wptr_offs];
401 volatile u32 *wb = (volatile u32 *)&adev->wb.wb[ring->wptr_offs];
722 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
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| amdgpu_gfx_v10_0.c | 286 uint64_t wptr_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
2809 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
2844 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
3029 wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
3138 adev->wb.wb[ring->wptr_offs] = 0;
3310 wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
4326 wptr = atomic_load_relaxed(&adev->wb.wb[ring->wptr_offs]);
4341 atomic_store_relaxed(&adev->wb.wb[ring->wptr_offs], ring->wptr);
4360 wptr = atomic_load_relaxed(&ring->adev->wb.wb[ring->wptr_offs]);
4372 atomic_store_relaxed(&adev->wb.wb[ring->wptr_offs], ring->wptr)
[all...] |
| amdgpu_uvd_v7_0.c | 128 return adev->wb.wb[ring->wptr_offs];
163 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr);
746 adev->wb.wb[adev->uvd.inst[i].ring_enc[0].wptr_offs] = 0;
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| amdgpu_gfx_v8_0.c | 4301 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
4388 uint64_t wptr_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
4505 wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
6024 return ring->adev->wb.wb[ring->wptr_offs];
6035 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr);
6235 return ring->adev->wb.wb[ring->wptr_offs];
6243 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr);
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| amdgpu_gfx_v9_0.c | 775 uint64_t wptr_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
3209 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
3418 wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
4858 wptr = atomic_load_relaxed(&adev->wb.wb[ring->wptr_offs]);
4873 atomic_store_relaxed(&adev->wb.wb[ring->wptr_offs], ring->wptr);
5047 wptr = atomic_load_relaxed(&ring->adev->wb.wb[ring->wptr_offs]);
5158 atomic_store_relaxed(&adev->wb.wb[ring->wptr_offs], ring->wptr);
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| amdgpu_gfx_v7_0.c | 2689 return ring->adev->wb.wb[ring->wptr_offs];
2697 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr);
2997 wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
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| /src/sys/external/bsd/drm2/dist/drm/radeon/ |
| radeon_cik.c | 4191 wptr = rdev->wb.wb[ring->wptr_offs/4];
4207 rdev->wb.wb[ring->wptr_offs/4] = ring->wptr;
8494 ring->wptr_offs = CIK_WB_CP1_WPTR_OFFSET;
8506 ring->wptr_offs = CIK_WB_CP2_WPTR_OFFSET;
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| radeon.h | 908 unsigned wptr_offs; member in struct:radeon_ring
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