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  /src/external/gpl3/gdb.old/dist/sim/common/
sim-hrw.c 41 return sim_core_write_buffer (sd, NULL, write_map,
sim-basics.h 57 write_map = 1, enumerator in enum:__anon21938
66 access_write = 1 << write_map,
sim-syscall.c 55 return sim_core_write_buffer (sd, cpu, write_map, buf, taddr, bytes);
cgen-mem.h 81 XCONCAT2 (sim_core_write_unaligned_,size) (cpu, pc, write_map, a, val); \
172 XCONCAT2 (sim_core_write_unaligned_,size) (cpu, pc, write_map, a, val); \
  /src/external/gpl3/gdb/dist/sim/common/
sim-hrw.c 41 return sim_core_write_buffer (sd, NULL, write_map,
sim-basics.h 57 write_map = 1, enumerator in enum:__anon1423
66 access_write = 1 << write_map,
sim-syscall.c 55 return sim_core_write_buffer (sd, cpu, write_map, buf, taddr, bytes);
cgen-mem.h 81 XCONCAT2 (sim_core_write_unaligned_,size) (cpu, pc, write_map, a, val); \
172 XCONCAT2 (sim_core_write_unaligned_,size) (cpu, pc, write_map, a, val); \
  /src/external/gpl3/gdb/dist/sim/mips/
sim-main.c 222 sim_core_write_aligned_16 (CPU, cia, write_map, pAddr, val);
226 sim_core_write_aligned_8 (CPU, cia, write_map, pAddr, MemElem);
229 sim_core_write_misaligned_7 (CPU, cia, write_map, pAddr, MemElem);
232 sim_core_write_misaligned_6 (CPU, cia, write_map, pAddr, MemElem);
235 sim_core_write_misaligned_5 (CPU, cia, write_map, pAddr, MemElem);
238 sim_core_write_aligned_4 (CPU, cia, write_map, pAddr, MemElem);
241 sim_core_write_misaligned_3 (CPU, cia, write_map, pAddr, MemElem);
244 sim_core_write_aligned_2 (CPU, cia, write_map, pAddr, MemElem);
247 sim_core_write_aligned_1 (CPU, cia, write_map, pAddr, MemElem);
  /src/external/gpl3/gdb.old/dist/sim/mips/
sim-main.c 222 sim_core_write_aligned_16 (CPU, cia, write_map, pAddr, val);
226 sim_core_write_aligned_8 (CPU, cia, write_map, pAddr, MemElem);
229 sim_core_write_misaligned_7 (CPU, cia, write_map, pAddr, MemElem);
232 sim_core_write_misaligned_6 (CPU, cia, write_map, pAddr, MemElem);
235 sim_core_write_misaligned_5 (CPU, cia, write_map, pAddr, MemElem);
238 sim_core_write_aligned_4 (CPU, cia, write_map, pAddr, MemElem);
241 sim_core_write_misaligned_3 (CPU, cia, write_map, pAddr, MemElem);
244 sim_core_write_aligned_2 (CPU, cia, write_map, pAddr, MemElem);
247 sim_core_write_aligned_1 (CPU, cia, write_map, pAddr, MemElem);
  /src/external/gpl3/gdb.old/dist/sim/microblaze/
microblaze.h 62 #define MEM_WR_BYTE(X, D) sim_core_write_1 (cpu, 0, write_map, X, D)
63 #define MEM_WR_HALF(X, D) sim_core_write_2 (cpu, 0, write_map, X, D)
64 #define MEM_WR_WORD(X, D) sim_core_write_4 (cpu, 0, write_map, X, D)
  /src/external/gpl3/gdb/dist/sim/microblaze/
microblaze.h 62 #define MEM_WR_BYTE(X, D) sim_core_write_1 (cpu, 0, write_map, X, D)
63 #define MEM_WR_HALF(X, D) sim_core_write_2 (cpu, 0, write_map, X, D)
64 #define MEM_WR_WORD(X, D) sim_core_write_4 (cpu, 0, write_map, X, D)
  /src/external/gpl3/gdb.old/dist/sim/aarch64/
memory.c 97 sim_core_write_unaligned_##N (cpu, 0, write_map, address, value); \
116 sim_core_write_unaligned_8 (cpu, 0, write_map, address, a.v[0]);
117 sim_core_write_unaligned_8 (cpu, 0, write_map, address + 8, a.v[1]);
  /src/external/gpl3/gdb/dist/sim/aarch64/
memory.c 97 sim_core_write_unaligned_##N (cpu, 0, write_map, address, value); \
116 sim_core_write_unaligned_8 (cpu, 0, write_map, address, a.v[0]);
117 sim_core_write_unaligned_8 (cpu, 0, write_map, address + 8, a.v[1]);
  /src/external/gpl3/gdb/dist/sim/mn10300/
mn10300-sim.h 161 PC, write_map, (ADDR), (DATA))
166 PC, write_map, (ADDR), (DATA))
171 PC, write_map, (ADDR), (DATA))
174 PC, write_map, (ADDR), dw2u64 (DATA))
  /src/external/gpl3/gdb.old/dist/sim/mn10300/
mn10300-sim.h 161 PC, write_map, (ADDR), (DATA))
166 PC, write_map, (ADDR), (DATA))
171 PC, write_map, (ADDR), (DATA))
174 PC, write_map, (ADDR), dw2u64 (DATA))
  /src/external/mit/isl/dist/
isl_flow.c 641 struct isl_map *write_map; local
647 write_map = isl_map_copy(acc->source[j].map);
648 write_map = isl_map_reverse(write_map);
649 dep_map = isl_map_apply_range(read_map, write_map);
673 struct isl_map *write_map; local
681 write_map = isl_map_copy(acc->source[k].map);
683 write_map = isl_map_reverse(write_map);
684 dep_map = isl_map_apply_range(read_map, write_map);
787 isl_map *write_map; local
815 isl_map *write_map; local
926 isl_map *write_map; local
    [all...]
  /src/external/gpl3/gdb.old/dist/sim/bfin/
bfin-sim.h 319 __cnt = sim_core_write_buffer (CPU_STATE(cpu), cpu, write_map, \
323 BFIN_TRACE_CORE (cpu, __taddr, __bytes, write_map, __v); \
377 map == write_map ? "STORE" : "FETCH", \
  /src/external/gpl3/gdb.old/dist/sim/example-synacor/
sim-main.c 119 sim_core_write_aligned_2 (cpu, pc, write_map, example_cpu->sp, num2);
413 sim_core_write_aligned_2 (cpu, pc, write_map, num2, num3);
431 sim_core_write_aligned_2 (cpu, pc, write_map, example_cpu->sp, (pc + 4) >> 1);
  /src/external/gpl3/gdb.old/dist/sim/pru/
interp.c 159 sim_core_signal (CPU_STATE (cpu), cpu, PC_byteaddr, write_map, local
166 sim_core_signal (CPU_STATE (cpu), cpu, PC_byteaddr, write_map, local
183 write_map,
  /src/external/gpl3/gdb/dist/sim/bfin/
bfin-sim.h 319 __cnt = sim_core_write_buffer (CPU_STATE(cpu), cpu, write_map, \
323 BFIN_TRACE_CORE (cpu, __taddr, __bytes, write_map, __v); \
377 map == write_map ? "STORE" : "FETCH", \
  /src/external/gpl3/gdb/dist/sim/example-synacor/
sim-main.c 119 sim_core_write_aligned_2 (cpu, pc, write_map, example_cpu->sp, num2);
413 sim_core_write_aligned_2 (cpu, pc, write_map, num2, num3);
431 sim_core_write_aligned_2 (cpu, pc, write_map, example_cpu->sp, (pc + 4) >> 1);
  /src/external/gpl3/gdb/dist/sim/pru/
interp.c 159 sim_core_signal (CPU_STATE (cpu), cpu, PC_byteaddr, write_map, local
166 sim_core_signal (CPU_STATE (cpu), cpu, PC_byteaddr, write_map, local
183 write_map,
  /src/external/gpl3/gdb.old/dist/sim/moxie/
interp.c 153 sim_core_write_aligned_1 (scpu, cia, write_map, x, v);
163 sim_core_write_aligned_2 (scpu, cia, write_map, x, v);
173 sim_core_write_aligned_4 (scpu, cia, write_map, x, v);
955 sim_core_write_buffer (sd, scpu, write_map, buf,
1283 sim_core_write_buffer (sd, scpu, write_map, buf, 0xE0000000, size);
1325 sim_core_write_buffer (sd, scpu, write_map, argv[i],
  /src/external/gpl3/gdb/dist/sim/moxie/
interp.c 153 sim_core_write_aligned_1 (scpu, cia, write_map, x, v);
163 sim_core_write_aligned_2 (scpu, cia, write_map, x, v);
173 sim_core_write_aligned_4 (scpu, cia, write_map, x, v);
955 sim_core_write_buffer (sd, scpu, write_map, buf,
1283 sim_core_write_buffer (sd, scpu, write_map, buf, 0xE0000000, size);
1325 sim_core_write_buffer (sd, scpu, write_map, argv[i],

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