HomeSort by: relevance | last modified time | path
    Searched refs:write_mlmbreg (Results 1 - 11 of 11) sorted by relevancy

  /src/sys/arch/arm/marvell/
mv78xx0.c 108 write_mlmbreg(MV78XX0_ICI_IRQIMER, 0);
109 write_mlmbreg(MV78XX0_ICI_IRQIMLR, 0);
110 write_mlmbreg(MV78XX0_ICI_IRQIMHR, 0);
113 write_mlmbreg(MVSOC_MLMB_MLMBIMR, 0);
141 write_mlmbreg(MV78XX0_ICI_IRQIMR(group),
151 write_mlmbreg(MV78XX0_ICI_IRQIMR(group),
168 write_mlmbreg(MVSOC_MLMB_MLMBIMR, mlmbim);
mvsoc_intr.c 114 write_mlmbreg(MVSOC_MLMB_MLMBICR,
116 write_mlmbreg(MVSOC_MLMB_MLMBIMR,
126 write_mlmbreg(MVSOC_MLMB_MLMBIMR,
orion.c 96 write_mlmbreg(ORION_MLMB_MIRQIMR, 0);
99 write_mlmbreg(MVSOC_MLMB_MLMBIMR, 0);
132 write_mlmbreg(ORION_MLMB_MIRQIMR,
141 write_mlmbreg(ORION_MLMB_MIRQIMR,
kirkwood.c 127 write_mlmbreg(KIRKWOOD_MLMB_MIRQIMLR, 0);
128 write_mlmbreg(KIRKWOOD_MLMB_MIRQIMHR, 0);
131 write_mlmbreg(MVSOC_MLMB_MLMBIMR, 0);
174 write_mlmbreg(reg, read_mlmbreg(reg) | irq_mask);
186 write_mlmbreg(reg, read_mlmbreg(reg) & ~irq_mask);
pci_machdep.c 490 write_mlmbreg(MVSOC_MLMB_WCR(window),
492 write_mlmbreg(MVSOC_MLMB_WBR(window), pcicfg_addr);
495 write_mlmbreg(MVSOC_MLMB_WRLR(window), pcicfg_addr);
496 write_mlmbreg(MVSOC_MLMB_WRHR(window), 0);
506 write_mlmbreg(MVSOC_MLMB_WCR(window),
511 write_mlmbreg(MVSOC_MLMB_WBR(window), base);
513 write_mlmbreg(MVSOC_MLMB_WRLR(window), remapl);
514 write_mlmbreg(MVSOC_MLMB_WRHR(window), remaph);
mvsocvar.h 53 #define write_mlmbreg(o, v) \ macro
armadaxp.c 931 write_mlmbreg(ARMADAXP_L2_CFU, reg);
1089 write_mlmbreg(MVSOC_MLMB_CIB_CTRL_CFG, reg);
1094 write_mlmbreg(MVSOC_MLMB_CFU_FAB_CTRL, reg);
1103 write_mlmbreg(MVSOC_MLMB_CFU_CFG, reg);
1140 write_mlmbreg(MVSOC_MLMB_WCR(i), reg);
1141 write_mlmbreg(MVSOC_MLMB_WBR(i), 0);
1153 write_mlmbreg(MVSOC_MLMB_WBR(def->window), reg);
1163 write_mlmbreg(MVSOC_MLMB_WCR(def->window), reg);
mvsoctmr.c 172 write_mlmbreg(MVSOC_MLMB_MLMBICR,
175 write_mlmbreg(MVSOC_MLMB_RSTOUTNMASKR,
dove.c 56 #define write_dbreg write_mlmbreg
174 write_mlmbreg(MVSOC_MLMB_MLMBIMR, 0);
  /src/sys/arch/evbarm/armadaxp/
armadaxp_machdep.c 256 write_mlmbreg(MVSOC_MLMB_WCR(window),
261 write_mlmbreg(MVSOC_MLMB_WBR(window),
265 write_mlmbreg(MVSOC_MLMB_WRLR(window),
267 write_mlmbreg(MVSOC_MLMB_WRHR(window), 0);
281 write_mlmbreg(MVSOC_MLMB_WCR(window),
286 write_mlmbreg(MVSOC_MLMB_WBR(window),
290 write_mlmbreg(MVSOC_MLMB_WRLR(window),
292 write_mlmbreg(MVSOC_MLMB_WRHR(window), 0);
  /src/sys/arch/evbarm/marvell/
marvell_machdep.c 144 write_mlmbreg(MVSOC_MLMB_WCR(window),
149 write_mlmbreg(MVSOC_MLMB_WBR(window),
153 write_mlmbreg(MVSOC_MLMB_WRLR(window),
155 write_mlmbreg(MVSOC_MLMB_WRHR(window), 0);
159 write_mlmbreg(MVSOC_MLMB_WCR(window),
164 write_mlmbreg(MVSOC_MLMB_WBR(window),
168 write_mlmbreg(MVSOC_MLMB_WRLR(window),
170 write_mlmbreg(MVSOC_MLMB_WRHR(window), 0);
180 write_mlmbreg(MVSOC_MLMB_RSTOUTNMASKR,
183 write_mlmbreg(MVSOC_MLMB_SSRR, MVSOC_MLMB_SSRR_SYSTEMSOFTRST)
    [all...]

Completed in 26 milliseconds