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    Searched refs:writer_wm_sets (Results 1 - 5 of 5) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/display/amdgpu_dm/
amdgpu_dm_pp_smu.c 580 if (ranges->writer_wm_sets[i].wm_inst > 3)
584 ranges->writer_wm_sets[i].wm_inst;
586 ranges->writer_wm_sets[i].max_fill_clk_mhz * 1000;
588 ranges->writer_wm_sets[i].min_fill_clk_mhz * 1000;
590 ranges->writer_wm_sets[i].max_drain_clk_mhz * 1000;
592 ranges->writer_wm_sets[i].min_drain_clk_mhz * 1000;
700 if (ranges->writer_wm_sets[i].wm_inst > 3)
704 ranges->writer_wm_sets[i].wm_inst;
706 ranges->writer_wm_sets[i].max_fill_clk_mhz * 1000;
708 ranges->writer_wm_sets[i].min_fill_clk_mhz * 1000
    [all...]
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/
dm_pp_smu.h 95 struct pp_smu_wm_set_range writer_wm_sets[MAX_WATERMARK_SETS]; member in struct:pp_smu_wm_range_sets
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/calcs/
amdgpu_dcn_calcs.c 1534 ranges.writer_wm_sets[0].wm_inst = WM_A;
1535 ranges.writer_wm_sets[0].min_fill_clk_mhz = socclk_khz / 1000;
1536 ranges.writer_wm_sets[0].max_fill_clk_mhz = overdrive / 1000;
1537 ranges.writer_wm_sets[0].min_drain_clk_mhz = min_fclk_khz / 1000;
1538 ranges.writer_wm_sets[0].max_drain_clk_mhz = overdrive / 1000;
1546 ranges.writer_wm_sets[0].wm_inst = WM_A;
1547 ranges.writer_wm_sets[0].min_fill_clk_mhz = 200;
1548 ranges.writer_wm_sets[0].max_fill_clk_mhz = 5000;
1549 ranges.writer_wm_sets[0].min_drain_clk_mhz = 800;
1550 ranges.writer_wm_sets[0].max_drain_clk_mhz = 5000
    [all...]
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/clk_mgr/dcn21/
amdgpu_rn_clk_mgr.c 462 ranges->writer_wm_sets[0].wm_inst = WM_A;
463 ranges->writer_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
464 ranges->writer_wm_sets[0].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
465 ranges->writer_wm_sets[0].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
466 ranges->writer_wm_sets[0].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn20/
amdgpu_dcn20_resource.c 3657 ranges.writer_wm_sets[0].wm_inst = 0;
3658 ranges.writer_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
3659 ranges.writer_wm_sets[0].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
3660 ranges.writer_wm_sets[0].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
3661 ranges.writer_wm_sets[0].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;

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