| /src/tests/lib/libc/locale/ |
| ducet_test.h | 44 {0x0338, 0x0334, 0x0},
45 {0x0336, 0x0334, 0x0},
46 {0x0337, 0x0334, 0x0},
47 {0x20D8, 0x0334, 0x0},
48 {0x20D9, 0x0334, 0x0},
49 {0x20DA, 0x0334, 0x0},
50 {0x20E5, 0x0334, 0x0},
51 {0x20EA, 0x0334, 0x0},
52 {0x20EB, 0x0334, 0x0},
53 {0x1BC9E, 0x0334, 0x0},
[all...] |
| /src/lib/libc/arch/sparc64/gdtoa/ |
| gd_qnan.h | 5 #define d_QNAN1 0x0
7 #define ld_QNAN1 0x0
8 #define ld_QNAN2 0x0
9 #define ld_QNAN3 0x0
|
| /src/lib/libc/arch/riscv/gdtoa/ |
| gd_qnan.h | 14 #define d_QNAN0 0x0
16 #define ld_QNAN0 0x0
17 #define ld_QNAN1 0x0
18 #define ld_QNAN2 0x0
|
| /src/lib/libc/arch/aarch64/gdtoa/ |
| gd_qnan.h | 6 #define d_QNAN1 0x0
8 #define ld_QNAN1 0x0
9 #define ld_QNAN2 0x0
10 #define ld_QNAN3 0x0
12 #define d_QNAN0 0x0
14 #define ld_QNAN0 0x0
15 #define ld_QNAN1 0x0
16 #define ld_QNAN2 0x0
|
| /src/lib/libc/arch/mips/gdtoa/ |
| gd_qnan.h | 8 #define d_QNAN1 0x0
10 #define ld_QNAN1 0x0
11 #define ld_QNAN2 0x0
12 #define ld_QNAN3 0x0
14 #define d_QNAN0 0x0
16 #define ld_QNAN0 0x0
17 #define ld_QNAN1 0x0
18 #define ld_QNAN2 0x0
|
| /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/mp/ |
| mp_11_0_sh_mask.h | 30 #define MP0_SMN_C2PMSG_32__CONTENT__SHIFT 0x0
33 #define MP0_SMN_C2PMSG_33__CONTENT__SHIFT 0x0
36 #define MP0_SMN_C2PMSG_34__CONTENT__SHIFT 0x0
39 #define MP0_SMN_C2PMSG_35__CONTENT__SHIFT 0x0
42 #define MP0_SMN_C2PMSG_36__CONTENT__SHIFT 0x0
45 #define MP0_SMN_C2PMSG_37__CONTENT__SHIFT 0x0
48 #define MP0_SMN_C2PMSG_38__CONTENT__SHIFT 0x0
51 #define MP0_SMN_C2PMSG_39__CONTENT__SHIFT 0x0
54 #define MP0_SMN_C2PMSG_40__CONTENT__SHIFT 0x0
57 #define MP0_SMN_C2PMSG_41__CONTENT__SHIFT 0x0
[all...] |
| mp_9_0_sh_mask.h | 29 #define MP0_SMN_C2PMSG_32__CONTENT__SHIFT 0x0
32 #define MP0_SMN_C2PMSG_33__CONTENT__SHIFT 0x0
35 #define MP0_SMN_C2PMSG_34__CONTENT__SHIFT 0x0
38 #define MP0_SMN_C2PMSG_35__CONTENT__SHIFT 0x0
41 #define MP0_SMN_C2PMSG_36__CONTENT__SHIFT 0x0
44 #define MP0_SMN_C2PMSG_37__CONTENT__SHIFT 0x0
47 #define MP0_SMN_C2PMSG_38__CONTENT__SHIFT 0x0
50 #define MP0_SMN_C2PMSG_39__CONTENT__SHIFT 0x0
53 #define MP0_SMN_C2PMSG_40__CONTENT__SHIFT 0x0
56 #define MP0_SMN_C2PMSG_41__CONTENT__SHIFT 0x0
[all...] |
| mp_10_0_sh_mask.h | 29 #define MP0_SMN_C2PMSG_32__CONTENT__SHIFT 0x0
32 #define MP0_SMN_C2PMSG_33__CONTENT__SHIFT 0x0
35 #define MP0_SMN_C2PMSG_34__CONTENT__SHIFT 0x0
38 #define MP0_SMN_C2PMSG_35__CONTENT__SHIFT 0x0
41 #define MP0_SMN_C2PMSG_36__CONTENT__SHIFT 0x0
44 #define MP0_SMN_C2PMSG_37__CONTENT__SHIFT 0x0
47 #define MP0_SMN_C2PMSG_38__CONTENT__SHIFT 0x0
50 #define MP0_SMN_C2PMSG_39__CONTENT__SHIFT 0x0
53 #define MP0_SMN_C2PMSG_40__CONTENT__SHIFT 0x0
56 #define MP0_SMN_C2PMSG_41__CONTENT__SHIFT 0x0
[all...] |
| mp_12_0_0_sh_mask.h | 29 #define MP0_SMN_C2PMSG_32__CONTENT__SHIFT 0x0
32 #define MP0_SMN_C2PMSG_33__CONTENT__SHIFT 0x0
35 #define MP0_SMN_C2PMSG_34__CONTENT__SHIFT 0x0
38 #define MP0_SMN_C2PMSG_35__CONTENT__SHIFT 0x0
41 #define MP0_SMN_C2PMSG_36__CONTENT__SHIFT 0x0
44 #define MP0_SMN_C2PMSG_37__CONTENT__SHIFT 0x0
47 #define MP0_SMN_C2PMSG_38__CONTENT__SHIFT 0x0
50 #define MP0_SMN_C2PMSG_39__CONTENT__SHIFT 0x0
53 #define MP0_SMN_C2PMSG_40__CONTENT__SHIFT 0x0
56 #define MP0_SMN_C2PMSG_41__CONTENT__SHIFT 0x0
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/smuio/ |
| smuio_9_0_sh_mask.h | 29 #define ROM_CNTL__CLOCK_GATING_EN__SHIFT 0x0
32 #define ROM_STATUS__ROM_BUSY__SHIFT 0x0
35 #define CGTT_ROM_CLK_CTRL0__ON_DELAY__SHIFT 0x0
44 #define ROM_INDEX__ROM_INDEX__SHIFT 0x0
47 #define ROM_DATA__ROM_DATA__SHIFT 0x0
50 #define ROM_START__ROM_START__SHIFT 0x0
53 #define ROM_SW_CNTL__DATA_SIZE__SHIFT 0x0
60 #define ROM_SW_STATUS__ROM_SW_DONE__SHIFT 0x0
63 #define ROM_SW_COMMAND__ROM_SW_INSTRUCTION__SHIFT 0x0
68 #define ROM_SW_DATA_1__ROM_SW_DATA__SHIFT 0x0
[all...] |
| /src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/arm/ |
| foundation-v8-gicv3.dtsi | 13 ranges = <0x0 0x0 0x2f000000 0x100000>;
15 reg = <0x0 0x2f000000 0x0 0x10000>,
16 <0x0 0x2f100000 0x0 0x200000>,
17 <0x0 0x2c000000 0x0 0x2000>,
18 <0x0 0x2c010000 0x0 0x2000>
[all...] |
| /src/lib/libc/arch/hppa/gdtoa/ |
| gd_qnan.h | 5 #define d_QNAN1 0x0
8 #define ld_QNAN1 0x0
9 #define ld_QNAN2 0x0
10 #define ld_QNAN3 0x0
|
| /src/lib/libc/arch/i386/gdtoa/ |
| gd_qnan.h | 4 #define d_QNAN0 0x0
6 #define ldus_QNAN0 0x0
7 #define ldus_QNAN1 0x0
8 #define ldus_QNAN2 0x0
|
| /src/sys/arch/i386/stand/lib/ |
| boot_params.S | 8 .long 0x0
|
| /src/lib/libc/arch/x86_64/gdtoa/ |
| gd_qnan.h | 4 #define d_QNAN0 0x0
6 #define ld_QNAN0 0x0
9 #define ld_QNAN3 0x0
10 #define ldus_QNAN0 0x0
11 #define ldus_QNAN1 0x0
12 #define ldus_QNAN2 0x0
|
| /src/sys/dev/microcode/bnx/ |
| bnxfw.h | 48 static int bnx_COM_b06FwReleaseMinor = 0x0;
54 static int bnx_COM_b06FwDataLen = 0x0;
62 0xa000046, 0x0, 0x0,
64 0x6000f02, 0x0, 0x3, 0xc8,
65 0x32, 0x3, 0x0, 0x0,
66 0x0, 0x0, 0x0, 0x10
[all...] |
| /src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/ |
| imx51-pinfunc.h | 15 #define MX51_PAD_EIM_D16__AUD4_RXFS 0x05c 0x3f0 0x000 0x5 0x0
16 #define MX51_PAD_EIM_D16__AUD5_TXD 0x05c 0x3f0 0x8d8 0x7 0x0
17 #define MX51_PAD_EIM_D16__EIM_D16 0x05c 0x3f0 0x000 0x0 0x0
18 #define MX51_PAD_EIM_D16__GPIO2_0 0x05c 0x3f0 0x000 0x1 0x0
19 #define MX51_PAD_EIM_D16__I2C1_SDA 0x05c 0x3f0 0x9b4 0x4 0x0
20 #define MX51_PAD_EIM_D16__UART2_CTS 0x05c 0x3f0 0x000 0x3 0x0
21 #define MX51_PAD_EIM_D16__USBH2_DATA0 0x05c 0x3f0 0x000 0x2 0x0
22 #define MX51_PAD_EIM_D17__AUD5_RXD 0x060 0x3f4 0x8d4 0x7 0x0
23 #define MX51_PAD_EIM_D17__EIM_D17 0x060 0x3f4 0x000 0x0 0x
[all...] |
| imx27-phytec-phycard-s-som.dtsi | 48 MX27_PAD_SD3_CMD__FEC_TXD0 0x0
49 MX27_PAD_SD3_CLK__FEC_TXD1 0x0
50 MX27_PAD_ATA_DATA0__FEC_TXD2 0x0
51 MX27_PAD_ATA_DATA1__FEC_TXD3 0x0
52 MX27_PAD_ATA_DATA2__FEC_RX_ER 0x0
53 MX27_PAD_ATA_DATA3__FEC_RXD1 0x0
54 MX27_PAD_ATA_DATA4__FEC_RXD2 0x0
55 MX27_PAD_ATA_DATA5__FEC_RXD3 0x0
56 MX27_PAD_ATA_DATA6__FEC_MDIO 0x0
57 MX27_PAD_ATA_DATA7__FEC_MDC 0x0
[all...] |
| imx53-pinfunc.h | 15 #define MX53_PAD_GPIO_19__KPP_COL_5 0x020 0x348 0x840 0x0 0x0
16 #define MX53_PAD_GPIO_19__GPIO4_5 0x020 0x348 0x000 0x1 0x0
17 #define MX53_PAD_GPIO_19__CCM_CLKO 0x020 0x348 0x000 0x2 0x0
18 #define MX53_PAD_GPIO_19__SPDIF_OUT1 0x020 0x348 0x000 0x3 0x0
19 #define MX53_PAD_GPIO_19__RTC_CE_RTC_EXT_TRIG2 0x020 0x348 0x000 0x4 0x0
20 #define MX53_PAD_GPIO_19__ECSPI1_RDY 0x020 0x348 0x000 0x5 0x0
21 #define MX53_PAD_GPIO_19__FEC_TDATA_3 0x020 0x348 0x000 0x6 0x0
22 #define MX53_PAD_GPIO_19__SRC_INT_BOOT 0x020 0x348 0x000 0x7 0x0
23 #define MX53_PAD_KEY_COL0__KPP_COL_0 0x024 0x34c 0x000 0x0 0x
[all...] |
| imx6ull-pinfunc-snvs.h | 15 #define MX6ULL_PAD_BOOT_MODE0__GPIO5_IO10 0x0000 0x0044 0x0000 0x5 0x0
16 #define MX6ULL_PAD_BOOT_MODE1__GPIO5_IO11 0x0004 0x0048 0x0000 0x5 0x0
17 #define MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x0008 0x004C 0x0000 0x5 0x0
18 #define MX6ULL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x000C 0x0050 0x0000 0x5 0x0
19 #define MX6ULL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x0010 0x0054 0x0000 0x5 0x0
20 #define MX6ULL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x0014 0x0058 0x0000 0x5 0x0
21 #define MX6ULL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x0018 0x005C 0x0000 0x5 0x0
22 #define MX6ULL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x001C 0x0060 0x0000 0x5 0x0
23 #define MX6ULL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x0020 0x0064 0x0000 0x5 0x0
24 #define MX6ULL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x0024 0x0068 0x0000 0x5 0x0
[all...] |
| imx6sll-pinfunc.h | 17 #define MX6SLL_PAD_WDOG_B__WDOG1_B 0x0014 0x02DC 0x0000 0x0 0x0
18 #define MX6SLL_PAD_WDOG_B__WDOG1_RESET_B_DEB 0x0014 0x02DC 0x0000 0x1 0x0
19 #define MX6SLL_PAD_WDOG_B__UART5_RI_B 0x0014 0x02DC 0x0000 0x2 0x0
20 #define MX6SLL_PAD_WDOG_B__GPIO3_IO18 0x0014 0x02DC 0x0000 0x5 0x0
21 #define MX6SLL_PAD_REF_CLK_24M__XTALOSC_REF_CLK_24M 0x0018 0x02E0 0x0000 0x0 0x0
22 #define MX6SLL_PAD_REF_CLK_24M__I2C3_SCL 0x0018 0x02E0 0x068C 0x1 0x0
23 #define MX6SLL_PAD_REF_CLK_24M__PWM3_OUT 0x0018 0x02E0 0x0000 0x2 0x0
24 #define MX6SLL_PAD_REF_CLK_24M__USB_OTG2_ID 0x0018 0x02E0 0x0560 0x3 0x0
[all...] |
| imx6sx-pinfunc.h | 15 #define MX6SX_PAD_GPIO1_IO00__I2C1_SCL 0x0014 0x035C 0x07A8 0x0 0x1
16 #define MX6SX_PAD_GPIO1_IO00__USDHC1_VSELECT 0x0014 0x035C 0x0000 0x1 0x0
17 #define MX6SX_PAD_GPIO1_IO00__SPDIF_LOCK 0x0014 0x035C 0x0000 0x2 0x0
18 #define MX6SX_PAD_GPIO1_IO00__CCM_WAIT 0x0014 0x035C 0x0000 0x3 0x0
19 #define MX6SX_PAD_GPIO1_IO00__WDOG1_WDOG_ANY 0x0014 0x035C 0x0000 0x4 0x0
20 #define MX6SX_PAD_GPIO1_IO00__GPIO1_IO_0 0x0014 0x035C 0x0000 0x5 0x0
21 #define MX6SX_PAD_GPIO1_IO00__SNVS_HP_WRAPPER_VIO_5 0x0014 0x035C 0x0000 0x6 0x0
22 #define MX6SX_PAD_GPIO1_IO00__PHY_DTB_1 0x0014 0x035C 0x0000 0x7 0x0
23 #define MX6SX_PAD_GPIO1_IO01__I2C1_SDA 0x0018 0x0360 0x07AC 0x0 0x1
24 #define MX6SX_PAD_GPIO1_IO01__USDHC1_RESET_B 0x0018 0x0360 0x0000 0x1 0x0
[all...] |
| /src/sys/arch/aarch64/aarch64/ |
| pmap_page.S | 43 movk x0, #(AARCH64_DIRECTMAP_START >> 48), lsl #48
46 orr x0, x0, x1
49 add x4, x0, #PAGE_SIZE
56 1: dc zva, x0
57 add x0, x0, x3
58 cmp x0, x4
62 2: stnp xzr, xzr, [x0, #0]
63 stnp xzr, xzr, [x0, #16
[all...] |
| /src/lib/libc/arch/m68k/gdtoa/ |
| gd_qnan.h | 5 #define d_QNAN1 0x0
9 #define ld_QNAN2 0x0
|
| /src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/freescale/ |
| imx8mp-pinfunc.h | 15 #define MX8MP_IOMUXC_GPIO1_IO00__GPIO1_IO00 0x014 0x274 0x000 0x0 0x0
16 #define MX8MP_IOMUXC_GPIO1_IO00__CCM_ENET_PHY_REF_CLK_ROOT 0x014 0x274 0x000 0x1 0x0
17 #define MX8MP_IOMUXC_GPIO1_IO00__ISP_FL_TRIG_0 0x014 0x274 0x5D4 0x3 0x0
18 #define MX8MP_IOMUXC_GPIO1_IO00__CCM_EXT_CLK1 0x014 0x274 0x000 0x6 0x0
19 #define MX8MP_IOMUXC_GPIO1_IO01__GPIO1_IO01 0x018 0x278 0x000 0x0 0x0
20 #define MX8MP_IOMUXC_GPIO1_IO01__PWM1_OUT 0x018 0x278 0x000 0x1 0x0
21 #define MX8MP_IOMUXC_GPIO1_IO01__ISP_SHUTTER_TRIG_0 0x018 0x278 0x5DC 0x3 0x0
22 #define MX8MP_IOMUXC_GPIO1_IO01__CCM_EXT_CLK2 0x018 0x278 0x000 0x6 0x0
[all...] |
