| /src/sys/arch/powerpc/include/ |
| spr.h | 141 #define SPR_SPRG5 0x115 /* E4.. SPR General 5 */
|
| /src/sys/arch/hpcmips/dev/ |
| ite8181reg.h | 96 #define ITE8181_GUI_CC1R1 0x115
|
| /src/external/gpl3/binutils/dist/gprofng/src/ |
| hwc_arm64_amcc.h | 80 { I("page_walk_l1_stage2_hit", 0x115, STXT("Page walk, L1 stage-2 hit")) },
|
| hwc_arm_ampere_1.h | 113 { I("bpu_branch_no_hit", 0x115,
|
| /src/external/gpl3/binutils.old/dist/gprofng/src/ |
| hwc_arm64_amcc.h | 80 { I("page_walk_l1_stage2_hit", 0x115, STXT("Page walk, L1 stage-2 hit")) },
|
| hwc_arm_ampere_1.h | 113 { I("bpu_branch_no_hit", 0x115,
|
| /src/lib/libform/ |
| form.h | 109 #define REQ_NEXT_WORD (KEY_MAX + 0x115) /* go to the next word in
|
| /src/sys/arch/powerpc/include/oea/ |
| spr.h | 45 #define SPR_SCOMD 0x115 /* .... SCOM Data Register (970) */
|
| /src/external/gpl3/gdb/dist/gdb/testsuite/gdb.arch/ |
| amd64-entry-value-inline.S | 214 .long 0x115 # DW_AT_sibling
273 .uleb128 0xe # (DIE (0x115) DW_TAG_subprogram)
299 .byte 0 # end of children of DIE 0x115
|
| /src/external/gpl3/gdb.old/dist/gdb/testsuite/gdb.arch/ |
| amd64-entry-value-inline.S | 214 .long 0x115 # DW_AT_sibling
273 .uleb128 0xe # (DIE (0x115) DW_TAG_subprogram)
299 .byte 0 # end of children of DIE 0x115
|
| /src/sys/external/bsd/drm2/dist/include/drm/ |
| drm_dp_helper.h | 513 #define DP_LINK_RATE_SET 0x115 /* eDP 1.4 */
|
| /src/sys/external/gpl2/dts/dist/include/dt-bindings/input/ |
| linux-event-codes.h | 363 #define BTN_FORWARD 0x115
|
| /src/external/bsd/openldap/dist/libraries/libldap/ |
| t61.c | 217 0, 0x103, 0, 0, 0, 0x115, 0, 0x11f, 0, 0x12d, 0, 0, 0, 0, 0, 0x14f,
478 * x114 = xc6/x45, x115 = xc6/x65, x12c = xc6/x49, x12d = xc6/x69
|
| /src/sys/arch/powerpc/powerpc/ |
| db_disasm.c | 441 { 0x115, "sprg5" },
|
| /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/bif/ |
| bif_5_0_d.h | 423 #define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB 0x115
|
| /src/sys/dev/qbus/ |
| qfont.c | 97 ,0x00 ,0x00 ,0x112 ,0x113 ,0x114 ,0x115 ,0x116 ,0x117 /* 136 */
132 ,0x00 ,0x00 ,0x112 ,0x113 ,0x114 ,0x115 ,0x116 ,0x117 /* 136 */
|
| /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gca/ |
| gfx_8_0_enum.h | 405 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__2BLOCKS_2TO1__1BLOCK_2TO2= 0x115,
1605 SC_GRP1_DYN_SCLK_BUSY = 0x115,
2562 SQ_PERF_SEL_ATC_XNACK_ALL = 0x115,
3567 #define SQ_DPP_ROW_SR5 0x115
|
| gfx_8_1_enum.h | 405 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__2BLOCKS_2TO1__1BLOCK_2TO2= 0x115,
1623 SC_GRP1_DYN_SCLK_BUSY = 0x115,
2580 SQ_PERF_SEL_ATC_XNACK_ALL = 0x115,
3585 #define SQ_DPP_ROW_SR5 0x115
|
| /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gmc/ |
| gmc_7_1_d.h | 1178 #define ixMC_IO_DEBUG_DQB2H_RXPHASE_D1 0x115
|
| gmc_8_1_d.h | 1282 #define ixMC_IO_DEBUG_DQB2H_RXPHASE_D1 0x115
|
| /src/external/gpl3/binutils/dist/opcodes/ |
| sparc-opc.c | 2189 { "xmulx", F3F(2, 0x36, 0x115), F3F(~2, ~0x36, ~0x115), "1,2,d", 0, HWCAP_VIS3, 0, v9d },
|
| /src/external/gpl3/binutils.old/dist/opcodes/ |
| sparc-opc.c | 2189 { "xmulx", F3F(2, 0x36, 0x115), F3F(~2, ~0x36, ~0x115), "1,2,d", 0, HWCAP_VIS3, 0, v9d },
|
| /src/external/gpl3/gdb/dist/opcodes/ |
| sparc-opc.c | 2189 { "xmulx", F3F(2, 0x36, 0x115), F3F(~2, ~0x36, ~0x115), "1,2,d", 0, HWCAP_VIS3, 0, v9d },
|
| /src/external/gpl3/gdb.old/dist/opcodes/ |
| sparc-opc.c | 2189 { "xmulx", F3F(2, 0x36, 0x115), F3F(~2, ~0x36, ~0x115), "1,2,d", 0, HWCAP_VIS3, 0, v9d },
|
| /src/sys/lib/libkern/arch/hppa/ |
| milli.S | 1313 x115: sh3add %r26,%r26,%r1 ! sh1add %r1,%r26,%r1 ! b e_2t0a0 ! sh1add %r1,%r1,%r1 label
|
