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  /src/sys/external/gpl2/dts/dist/include/dt-bindings/clock/
lpc18xx-ccu.h 18 #define CLK_APB3_ADC0 0x118
omap5.h 82 #define OMAP5_GPIO8_CLKCTRL OMAP5_CLKCTRL_INDEX(0x118)
dra7.h 156 #define DRA7_L4PER_GPIO8_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x118)
  /src/sys/arch/ofppc/ofppc/
locore.S 109 mtspr 0x118,0 /* clear ASR[V] to enable segregs */
  /src/sys/arch/amiga/dev/
ioblix_zbus.c 92 { "com", 0x118, 24000000 },
  /src/sys/arch/arm/broadcom/
bcm2835_cm.h 149 #define CM_EVENT 0x118
  /src/sys/arch/arm/ixp12x0/
ixp12x0_pcireg.h 108 #define DRAM_ADDR_SIZE_2 0x118
  /src/sys/arch/arm/nvidia/
tegra124_xusbpadreg.h 102 #define XUSB_PADCTL_IOPHY_MISC_PAD_P4_CTL4_REG 0x118
  /src/sys/arch/sh3/include/
pcicreg.h 71 #define SH4_PCIINTM (SH4_PCIC+0x118) /* 32bit */
  /src/sys/dev/usb/
if_smscreg.h 145 #define SMSC_MII_DATA 0x118
if_muereg.h 77 #define MUE_RX_ADDRH 0x118
  /src/sys/arch/amiga/amiga/
cc_registers.h 166 #define R_BPL4DAT 0x118
  /src/sys/arch/arm/footbridge/
dc21285reg.h 181 #define SDRAM_ADDRESS_SIZE_2 0x118
  /src/sys/arch/arm/imx/
imx23_clkctrlreg.h 277 #define HW_CLKCTRL_CLKSEQ_CLR 0x118
  /src/sys/arch/arm/sunxi/
sun8i_v3s_ccu.c 66 #define TCON_CLK_REG 0x118
  /src/sys/arch/arm/ti/
if_cpswreg.h 44 #define CPSW_PORT_P_TX_PRI_MAP(p) (CPSW_PORT_OFFSET + 0x118 + ((p-1) * 0x100))
  /src/sys/arch/hpcmips/dev/
ite8181reg.h 99 #define ITE8181_GUI_CC2R0 0x118 /* Cursor Color 2 Reg. */
  /src/sys/arch/hpcmips/vr/
icureg.h 133 #define VR4181_KIUINT_REG_W 0x118 /* Level2 KIU intr reg */
  /src/sys/dev/ic/
ahcisatareg.h 218 #define AHCI_P_CMD(p) (0x118 + AHCI_P_OFFSET(p)) /* Port command/status */
igsfbreg.h 300 #define IGS_COP_SRC2_MAP_WIDTH_REG 0x118
  /src/sys/dev/isa/
addcom_isa.c 99 0x118,
  /src/sys/dev/pci/
cs4281reg.h 92 #define CS4281_DBA0 0x118 /* DMA Engine 0 Base Address Register */
  /src/sys/dev/sbus/
p9100reg.h 132 #define VID_HCNTPRLD 0x118 /* hcounter preload */
  /src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/nxp/imx/
imx25-pinfunc.h 292 #define MX25_PAD_CONTRAST__CONTRAST 0x118 0x310 0x000 0x00 0x000
293 #define MX25_PAD_CONTRAST__GPT4_CAPIN1 0x118 0x310 0x000 0x01 0x000
294 #define MX25_PAD_CONTRAST__CSPI2_SS1 0x118 0x310 0x4a8 0x02 0x000
295 #define MX25_PAD_CONTRAST__PWM4_PWMO 0x118 0x310 0x000 0x04 0x000
296 #define MX25_PAD_CONTRAST__FEC_CRS 0x118 0x310 0x508 0x05 0x001
297 #define MX25_PAD_CONTRAST__USBH2_PWR 0x118 0x310 0x000 0x06 0x000
imxrt1050-pinfunc.h 528 #define MXRT1050_IOMUXC_GPIO_AD_B1_07_FLEXSPI_B_DATA0 0x118 0x308 0x4B8 0x0 0x1
529 #define MXRT1050_IOMUXC_GPIO_AD_B1_07_LPI2C3_SCL 0x118 0x308 0x4DC 0x1 0x2
530 #define MXRT1050_IOMUXC_GPIO_AD_B1_07_LPUART3_RXD 0x118 0x308 0x538 0x2 0x1
531 #define MXRT1050_IOMUXC_GPIO_AD_B1_07_SPDIF_EXT_CLK 0x118 0x308 0x000 0x3 0x0
532 #define MXRT1050_IOMUXC_GPIO_AD_B1_07_CSI_HSYNC 0x118 0x308 0x420 0x4 0x1
533 #define MXRT1050_IOMUXC_GPIO_AD_B1_07_GPIO1_IO23 0x118 0x308 0x000 0x5 0x0
534 #define MXRT1050_IOMUXC_GPIO_AD_B1_07_USDHC2_DATA3 0x118 0x308 0x5F4 0x6 0x1
535 #define MXRT1050_IOMUXC_GPIO_AD_B1_07_KPP_COL04 0x118 0x308 0x000 0x7 0x0

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