HomeSort by: relevance | last modified time | path
    Searched refs:x118 (Results 1 - 25 of 108) sorted by relevancy

1 2 3 4 5

  /src/sys/external/gpl2/dts/dist/include/dt-bindings/clock/
lpc18xx-ccu.h 18 #define CLK_APB3_ADC0 0x118
omap5.h 82 #define OMAP5_GPIO8_CLKCTRL OMAP5_CLKCTRL_INDEX(0x118)
dra7.h 148 #define DRA7_GPIO8_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x118)
324 #define DRA7_L4PER_GPIO8_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x118)
  /src/sys/arch/ofppc/ofppc/
locore.S 109 mtspr 0x118,0 /* clear ASR[V] to enable segregs */
  /src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/
bcm21664.dtsi 66 reg = <0x3e000000 0x118>;
76 reg = <0x3e001000 0x118>;
86 reg = <0x3e002000 0x118>;
bcm23550.dtsi 134 reg = <0x00000000 0x118>;
144 reg = <0x00001000 0x118>;
154 reg = <0x00002000 0x118>;
omap4-panda-es.dts 62 OMAP4_IOPAD(0x118, PIN_INPUT_PULLUP | MUX_MODE0) /* uart2_cts.uart2_cts - HCI */
omap4-var-som-om44-wlan.dtsi 24 OMAP4_IOPAD(0x118, PIN_INPUT_PULLUP | MUX_MODE0) /* uart2_cts.uart2_cts */
  /src/sys/arch/amiga/dev/
ioblix_zbus.c 92 { "com", 0x118, 24000000 },
  /src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/broadcom/stingray/
stingray-pcie.dtsi 25 <0x118 &gic_its 0x2150 0x8>, /* PF2-VF16-23 */
  /src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/ti/
k3-am65-wakeup.dtsi 44 reg = <0x4301c000 0x118>;
  /src/sys/arch/arm/broadcom/
bcm2835_cm.h 149 #define CM_EVENT 0x118
  /src/sys/arch/arm/ixp12x0/
ixp12x0_pcireg.h 108 #define DRAM_ADDR_SIZE_2 0x118
  /src/sys/arch/arm/nvidia/
tegra124_xusbpadreg.h 102 #define XUSB_PADCTL_IOPHY_MISC_PAD_P4_CTL4_REG 0x118
  /src/sys/arch/sh3/include/
pcicreg.h 71 #define SH4_PCIINTM (SH4_PCIC+0x118) /* 32bit */
  /src/sys/dev/usb/
if_smscreg.h 145 #define SMSC_MII_DATA 0x118
  /src/sys/arch/amiga/amiga/
cc_registers.h 166 #define R_BPL4DAT 0x118
  /src/sys/arch/arm/footbridge/
dc21285reg.h 181 #define SDRAM_ADDRESS_SIZE_2 0x118
  /src/sys/arch/arm/imx/
imx23_clkctrlreg.h 277 #define HW_CLKCTRL_CLKSEQ_CLR 0x118
imx23_powerreg.h 359 #define HW_POWER_DEBUG_CLR 0x118
  /src/sys/arch/arm/sunxi/
sun8i_v3s_ccu.c 66 #define TCON_CLK_REG 0x118
  /src/sys/arch/arm/ti/
if_cpswreg.h 44 #define CPSW_PORT_P_TX_PRI_MAP(p) (CPSW_PORT_OFFSET + 0x118 + ((p-1) * 0x100))
  /src/sys/arch/hpcmips/vr/
icureg.h 133 #define VR4181_KIUINT_REG_W 0x118 /* Level2 KIU intr reg */
  /src/sys/dev/isa/
addcom_isa.c 99 0x118,
  /src/sys/dev/pci/
cs4281reg.h 92 #define CS4281_DBA0 0x118 /* DMA Engine 0 Base Address Register */

Completed in 44 milliseconds

1 2 3 4 5