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  /src/sys/external/gpl2/dts/dist/include/dt-bindings/clock/
lpc18xx-ccu.h 20 #define CLK_APB3_CAN0 0x128
omap4.h 121 #define OMAP4_MMC4_CLKCTRL OMAP4_CLKCTRL_INDEX(0x128)
omap5.h 84 #define OMAP5_MMC4_CLKCTRL OMAP5_CLKCTRL_INDEX(0x128)
  /src/external/bsd/wpa/dist/wpa_supplicant/wpa_gui-qt4/icons/
Makefile 4 SIZES := 16x16 22x22 32x32 48x48 64x64 128x128
  /src/external/gpl3/gcc/dist/libgcc/config/libbid/
bid_from_int.c 191 UINT128 x128, res128; local
227 x128.w[1] = 0x0;
228 x128.w[0] = x;
229 round128_19_38 (q, ind, x128, &res128, &incr_exp,
  /src/external/gpl3/gcc.old/dist/libgcc/config/libbid/
bid_from_int.c 191 UINT128 x128, res128; local
227 x128.w[1] = 0x0;
228 x128.w[0] = x;
229 round128_19_38 (q, ind, x128, &res128, &incr_exp,
  /src/sys/arch/arm/broadcom/
bcm2835_cm.h 153 #define CM_OSCFREQI 0x128
  /src/sys/arch/arm/ixp12x0/
ixp12x0_pcireg.h 112 #define I2O_OPH 0x128
  /src/sys/arch/arm/marvell/
mvsocreg.h 132 #define MVSOC_MLMB_L2CFG 0x128 /* L2 Cache Config */
  /src/sys/arch/arm/nvidia/
tegra124_xusbpadreg.h 106 #define XUSB_PADCTL_IOPHY_MISC_PAD_P2_CTL6_REG 0x128
tegra124_cpu.c 61 #define FUSE_GPU_IDDQ_REG 0x128
  /src/sys/dev/usb/
if_smscreg.h 149 #define SMSC_WUFF 0x128
  /src/external/gpl3/binutils/dist/include/opcode/
spu-insns.h 191 APUOP(M_BIZ, RR, 0x128, "biz", _A2(A_T,A_A), 00011, BR) /* BIZ IP<-RA_if(RT) */
386 APUOPFB(M_BIZD, RR, 0x128, 0x20, "bizd", _A2(A_T,A_A), 00011, BR) /* BIZ IP<-RA_if(RT) */
387 APUOPFB(M_BIZE, RR, 0x128, 0x10, "bize", _A2(A_T,A_A), 00011, BR) /* BIZ IP<-RA_if(RT) */
396 APUOP(M_BIF, RR, 0x128, "bif", _A2(A_T,A_A), 00011, BR) /* BIZ IP<-RA_if(RT) */
403 APUOPFB(M_BIFD, RR, 0x128, 0x20, "bifd", _A2(A_T,A_A), 00011, BR) /* BIZ IP<-RA_if(RT) */
404 APUOPFB(M_BIFE, RR, 0x128, 0x10, "bife", _A2(A_T,A_A), 00011, BR) /* BIZ IP<-RA_if(RT) */
  /src/external/gpl3/binutils.old/dist/include/opcode/
spu-insns.h 191 APUOP(M_BIZ, RR, 0x128, "biz", _A2(A_T,A_A), 00011, BR) /* BIZ IP<-RA_if(RT) */
386 APUOPFB(M_BIZD, RR, 0x128, 0x20, "bizd", _A2(A_T,A_A), 00011, BR) /* BIZ IP<-RA_if(RT) */
387 APUOPFB(M_BIZE, RR, 0x128, 0x10, "bize", _A2(A_T,A_A), 00011, BR) /* BIZ IP<-RA_if(RT) */
396 APUOP(M_BIF, RR, 0x128, "bif", _A2(A_T,A_A), 00011, BR) /* BIZ IP<-RA_if(RT) */
403 APUOPFB(M_BIFD, RR, 0x128, 0x20, "bifd", _A2(A_T,A_A), 00011, BR) /* BIZ IP<-RA_if(RT) */
404 APUOPFB(M_BIFE, RR, 0x128, 0x10, "bife", _A2(A_T,A_A), 00011, BR) /* BIZ IP<-RA_if(RT) */
  /src/external/gpl3/gdb.old/dist/include/opcode/
spu-insns.h 191 APUOP(M_BIZ, RR, 0x128, "biz", _A2(A_T,A_A), 00011, BR) /* BIZ IP<-RA_if(RT) */
386 APUOPFB(M_BIZD, RR, 0x128, 0x20, "bizd", _A2(A_T,A_A), 00011, BR) /* BIZ IP<-RA_if(RT) */
387 APUOPFB(M_BIZE, RR, 0x128, 0x10, "bize", _A2(A_T,A_A), 00011, BR) /* BIZ IP<-RA_if(RT) */
396 APUOP(M_BIF, RR, 0x128, "bif", _A2(A_T,A_A), 00011, BR) /* BIZ IP<-RA_if(RT) */
403 APUOPFB(M_BIFD, RR, 0x128, 0x20, "bifd", _A2(A_T,A_A), 00011, BR) /* BIZ IP<-RA_if(RT) */
404 APUOPFB(M_BIFE, RR, 0x128, 0x10, "bife", _A2(A_T,A_A), 00011, BR) /* BIZ IP<-RA_if(RT) */
  /src/external/gpl3/gdb/dist/include/opcode/
spu-insns.h 191 APUOP(M_BIZ, RR, 0x128, "biz", _A2(A_T,A_A), 00011, BR) /* BIZ IP<-RA_if(RT) */
386 APUOPFB(M_BIZD, RR, 0x128, 0x20, "bizd", _A2(A_T,A_A), 00011, BR) /* BIZ IP<-RA_if(RT) */
387 APUOPFB(M_BIZE, RR, 0x128, 0x10, "bize", _A2(A_T,A_A), 00011, BR) /* BIZ IP<-RA_if(RT) */
396 APUOP(M_BIF, RR, 0x128, "bif", _A2(A_T,A_A), 00011, BR) /* BIZ IP<-RA_if(RT) */
403 APUOPFB(M_BIFD, RR, 0x128, 0x20, "bifd", _A2(A_T,A_A), 00011, BR) /* BIZ IP<-RA_if(RT) */
404 APUOPFB(M_BIFE, RR, 0x128, 0x10, "bife", _A2(A_T,A_A), 00011, BR) /* BIZ IP<-RA_if(RT) */
  /src/sys/arch/amiga/amiga/
cc_registers.h 174 #define R_SPR2PTH 0x128
  /src/sys/arch/arm/amlogic/
meson_thermal.c 82 .aosec_reg = 0x128
  /src/sys/arch/arm/footbridge/
dc21285reg.h 188 #define I2O_OUTBOUND_POST_HEAD 0x128
  /src/sys/arch/arm/imx/
imx23_icollreg.h 242 #define HW_ICOLL_INTERRUPT0_CLR 0x128
  /src/sys/arch/arm/ti/
omap2_gpmcreg.h 87 #define GPMC_CONFIG3_4 0x128
  /src/sys/dev/ic/
ahcisatareg.h 265 #define AHCI_P_SSTS(p) (0x128 + AHCI_P_OFFSET(p)) /* Serial ATA status */
  /src/sys/dev/isa/
addcom_isa.c 101 0x128,
  /src/sys/dev/pci/
cs4281reg.h 96 #define CS4281_DBA1 0x128 /* DMA Engine 1 Base Address Register */
  /src/sys/dev/sbus/
p9100reg.h 136 #define VID_VBRE 0x128 /* vblank raising edge */

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