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  /src/sys/arch/mips/alchemy/dev/
com_aubus_reg.h 16 #define AUCOM_LCTL 0x14 /* line control register (R/W) */
17 #define AUCOM_CFCR 0x14 /* line control register (R/W) */
augpioreg.h 52 #define AUGPIO_SIZE 0x14
59 #define AUGPIO2_ENABLE 0x14
aupscreg.h 90 #define AUPSC_STAT 0x14
104 #define AUPSC_SPISTAT 0x14 /* Read only */
114 #define AUPSC_I2SSTAT 0x14 /* Read only */
125 #define AUPSC_AC97STAT 0x14 /* Read only */
139 #define AUPSC_SMBSTAT 0x14 /* Read only */
  /src/sys/dev/pci/
if_pcnreg.h 64 #define PCN16_RESET 0x14
73 #define PCN32_RAP 0x14
amdpmreg.h 48 #define NFORCE_PMPTR 0x14 /* nForce System Management IO space */
  /src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/
imx7d-pico-pi.dts 70 MX7D_PAD_EPDC_DATA00__GPIO2_IO0 0x14
71 MX7D_PAD_EPDC_DATA01__GPIO2_IO1 0x14
72 MX7D_PAD_EPDC_DATA02__GPIO2_IO2 0x14
73 MX7D_PAD_EPDC_DATA03__GPIO2_IO3 0x14
74 MX7D_PAD_EPDC_DATA05__GPIO2_IO5 0x14
75 MX7D_PAD_EPDC_DATA12__GPIO2_IO12 0x14
76 MX7D_PAD_EPDC_DATA07__GPIO2_IO7 0x14
82 MX7D_PAD_EPDC_DATA06__GPIO2_IO6 0x14
88 MX7D_PAD_EPDC_DATA04__GPIO2_IO4 0x14
89 MX7D_PAD_EPDC_DATA13__GPIO2_IO13 0x14
    [all...]
imx7-colibri.dtsi 493 MX7D_PAD_SAI1_RX_SYNC__GPIO6_IO16 0x14 /* SODIMM 77 */
494 MX7D_PAD_EPDC_DATA09__GPIO2_IO9 0x14 /* SODIMM 89 */
496 MX7D_PAD_LCD_RESET__GPIO3_IO4 0x14 /* SODIMM 93 */
497 MX7D_PAD_EPDC_DATA13__GPIO2_IO13 0x14 /* SODIMM 95 */
498 MX7D_PAD_ENET1_RGMII_TXC__GPIO7_IO11 0x14 /* SODIMM 99 */
500 MX7D_PAD_EPDC_DATA00__GPIO2_IO0 0x14 /* SODIMM 111 */
501 MX7D_PAD_EPDC_DATA01__GPIO2_IO1 0x14 /* SODIMM 113 */
502 MX7D_PAD_EPDC_DATA02__GPIO2_IO2 0x14 /* SODIMM 115 */
503 MX7D_PAD_EPDC_DATA03__GPIO2_IO3 0x14 /* SODIMM 117 */
504 MX7D_PAD_EPDC_DATA04__GPIO2_IO4 0x14 /* SODIMM 119 *
    [all...]
imx7d-pico-hobbit.dts 90 MX7D_PAD_EPDC_DATA00__GPIO2_IO0 0x14
91 MX7D_PAD_EPDC_DATA01__GPIO2_IO1 0x14
92 MX7D_PAD_EPDC_DATA02__GPIO2_IO2 0x14
93 MX7D_PAD_EPDC_DATA03__GPIO2_IO3 0x14
94 MX7D_PAD_EPDC_DATA05__GPIO2_IO5 0x14
95 MX7D_PAD_EPDC_DATA12__GPIO2_IO12 0x14
96 MX7D_PAD_EPDC_DATA07__GPIO2_IO7 0x14
102 MX7D_PAD_EPDC_DATA13__GPIO2_IO13 0x14
  /src/sys/external/bsd/drm2/dist/drm/radeon/
radeon_rv770_smc.c 204 0x0C, 0x14, 0x0C, 0x14,
205 0x0C, 0x14, 0x0C, 0x14,
206 0x0C, 0x14, 0x0C, 0x14,
207 0x0C, 0x14, 0x0C, 0x14,
208 0x0C, 0x14, 0x0C, 0x14,
    [all...]
  /src/sys/arch/arm/marvell/
mvsoctmrreg.h 35 #define MVSOCTMR_TIMER(n) (0x14 + (n) * 8)/* CPU Timer(n) */
mvsocrtcreg.h 55 #define MVSOCRTC_INTCAUSE 0x14
  /src/sys/arch/arm/sa11x0/
sa11x0_gpioreg.h 53 #define SAGPIO_FER 0x14
sa11x0_ostreg.h 45 #define SAOST_SR 0x14
  /src/sys/arch/arm/ti/
ti_rngreg.h 37 #define TRNG_CONTROL_REG 0x14
  /src/sys/arch/evbmips/mipssim/
if_mipsnetreg.h 41 #define MN_INTR 0x14 /* interrupt control */
  /src/sys/arch/i386/pci/
gscpcibreg.h 32 #define GSCGPIO_GPDI1 0x14
  /src/sys/external/bsd/drm2/include/video/
mipi_display.h 40 #define MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM 0x14
  /src/sys/dev/onewire/
onewiredevs.h 19 #define ONEWIRE_FAMILY_DS2430 0x14
  /src/sys/arch/hpcmips/vr/
vrgiureg.h 57 #define GIUINTALSEL_REG 0x14
58 #define GIUINTALSEL_L_REG_W 0x14
vrkiureg.h 53 #define KIUWKS 0x14
  /src/sys/external/isc/libsodium/dist/src/libsodium/crypto_core/hsalsa20/ref2/
core_hsalsa20_ref2.c 23 x9, x10, x11, x12, x13, x14, x15; local in function:crypto_core_hsalsa20
44 x14 = LOAD32_LE(k + 28);
59 x14 ^= ROTL32(x10 + x6, 7);
60 x2 ^= ROTL32(x14 + x10, 9);
61 x6 ^= ROTL32(x2 + x14, 13);
79 x12 ^= ROTL32(x15 + x14, 7);
81 x14 ^= ROTL32(x13 + x12, 13);
82 x15 ^= ROTL32(x14 + x13, 18);
  /src/sys/arch/arm/amlogic/
meson_canvasreg.h 36 #define DC_CAV_LUT_ADDR_REG CANVAS_REG(0x14)
  /src/sys/arch/arm/nvidia/
tegra_rtcreg.h 37 #define RTC_SECONDS_ALARM0_REG 0x14
  /src/sys/netinet/
igmp.h 101 #define IGMP_PIM 0x14 /* PIM routing message */
  /src/sys/arch/luna68k/include/
lcd.h 63 #define LCDMOVE_C_RIGHT 0x14 /* cursor moves right */

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