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  /src/sys/arch/arm/nvidia/
tegra_pciereg.h 62 #define AFI_PEXBIAS_CTRL_REG 0x168
tegra210_pinmux.c 151 TEGRA_PIN("batt_bcl", 0x168, "bcl", "rsvd1", "rsvd2", "rsvd3"),
tegra_hdmireg.h 214 #define HDMI_NV_PDISP_SOR_CSTM_REG 0x168
  /src/sys/external/gpl2/dts/dist/include/dt-bindings/clock/
dm814.h 23 #define DM814_I2C2_CLKCTRL DM814_CLKCTRL_INDEX(0x168)
dm816.h 23 #define DM816_I2C2_CLKCTRL DM816_CLKCTRL_INDEX(0x168)
omap5.h 90 #define OMAP5_I2C5_CLKCTRL OMAP5_CLKCTRL_INDEX(0x168)
dra7.h 186 #define DRA7_L4PER2_MCASP3_CLKCTRL DRA7_L4PER2_CLKCTRL_INDEX(0x168)
  /src/sys/arch/sparc64/include/
trap.h 128 #define T_RTF_DEF_TRAP 0x168
  /src/sys/arch/arm/broadcom/
bcm2835_cm.h 127 #define CM_DFTCTL 0x168
  /src/tests/lib/libcurses/tests/
std_defines 87 assign KEY_END 0x168
  /src/sys/arch/amiga/amiga/
cc_registers.h 206 #define R_SPR5_POS 0x168
  /src/sys/arch/arm/footbridge/
dc21285reg.h 269 #define UART_H_UBRLCR 0x168
  /src/sys/arch/arm/ti/
omap2_gpmcreg.h 101 #define GPMC_CONFIG7_5 0x168
  /src/sys/arch/hppa/dev/
mem.c 137 uint32_t pad7[0x168]; /* 0x200 */
  /src/sys/arch/m68k/060sp/dist/
fplsp.doc 108 bsr.l _060FPLSP_TOP+0x168 # branch to frem routine
185 0x168: _060LSP__frems_
  /src/sys/dev/pci/
cs4281reg.h 112 #define CS4281_DMR3 0x168 /* DMA Engine 3 Mode Register */
  /src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/broadcom/stingray/
stingray-pinctrl.dtsi 228 0x168 MODE_NITRO /* ext_mdc */
  /src/lib/libcurses/
keyname.c 279 if (key == 0x168) {
  /src/sys/arch/arm/imx/
imx23_digctlreg.h 285 #define HW_DIGCTL_OCRAM_STATUS5_CLR 0x168
  /src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/nxp/imx/
imxrt1050-pinfunc.h 697 #define MXRT1050_IOMUXC_GPIO_B0_11_LCD_DATA07 0x168 0x358 0x000 0x0 0x0
698 #define MXRT1050_IOMUXC_GPIO_B0_11_TMR4_TIMER2 0x168 0x358 0x000 0x1 0x0
699 #define MXRT1050_IOMUXC_GPIO_B0_11_FLEXPWM2_PWM2_B 0x168 0x358 0x490 0x2 0x1
700 #define MXRT1050_IOMUXC_GPIO_B0_11_SAI1_TX_DATA02 0x168 0x358 0x59C 0x3 0x1
701 #define MXRT1050_IOMUXC_GPIO_B0_11_FLEXIO2_D11 0x168 0x358 0x000 0x4 0x0
702 #define MXRT1050_IOMUXC_GPIO_B0_11_GPIO2_IO11 0x168 0x358 0x000 0x5 0x0
703 #define MXRT1050_IOMUXC_GPIO_B0_11_SRC_BT_CFG07 0x168 0x358 0x000 0x6 0x0
imx6dl-pinfunc.h 426 #define MX6QDL_PAD_EIM_D25__EIM_DATA25 0x168 0x538 0x000 0x0 0x0
427 #define MX6QDL_PAD_EIM_D25__ECSPI4_SS3 0x168 0x538 0x000 0x1 0x0
428 #define MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x168 0x538 0x90c 0x2 0x1
429 #define MX6QDL_PAD_EIM_D25__UART3_TX_DATA 0x168 0x538 0x000 0x2 0x0
430 #define MX6QDL_PAD_EIM_D25__ECSPI1_SS3 0x168 0x538 0x7f0 0x3 0x0
431 #define MX6QDL_PAD_EIM_D25__ECSPI2_SS3 0x168 0x538 0x000 0x4 0x0
432 #define MX6QDL_PAD_EIM_D25__GPIO3_IO25 0x168 0x538 0x000 0x5 0x0
433 #define MX6QDL_PAD_EIM_D25__AUD5_RXC 0x168 0x538 0x7b8 0x6 0x1
434 #define MX6QDL_PAD_EIM_D25__UART1_DSR_B 0x168 0x538 0x000 0x7 0x0
435 #define MX6QDL_PAD_EIM_D25__EPDC_SDCE8 0x168 0x538 0x000 0x8 0x
    [all...]
  /src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/freescale/
imx8mm-pinfunc.h 315 #define MX8MM_IOMUXC_SAI1_RXD1_SAI1_RX_DATA1 0x168 0x3D0 0x000 0x0 0x0
316 #define MX8MM_IOMUXC_SAI1_RXD1_SAI5_RX_DATA1 0x168 0x3D0 0x4D8 0x1 0x1
317 #define MX8MM_IOMUXC_SAI1_RXD1_PDM_DATA1 0x168 0x3D0 0x538 0x3 0x1
318 #define MX8MM_IOMUXC_SAI1_RXD1_CORESIGHT_TRACE1 0x168 0x3D0 0x000 0x4 0x0
319 #define MX8MM_IOMUXC_SAI1_RXD1_GPIO4_IO3 0x168 0x3D0 0x000 0x5 0x0
320 #define MX8MM_IOMUXC_SAI1_RXD1_CCMSRCGPCMIX_BOOT_CFG1 0x168 0x3D0 0x000 0x6 0x0
321 #define MX8MM_IOMUXC_SAI1_RXD1_SIM_M_HADDR18 0x168 0x3D0 0x000 0x7 0x0
imx8mq-pinfunc.h 303 #define MX8MQ_IOMUXC_SAI1_RXD1_SAI1_RX_DATA1 0x168 0x3D0 0x000 0x0 0x0
304 #define MX8MQ_IOMUXC_SAI1_RXD1_SAI5_RX_DATA1 0x168 0x3D0 0x4D8 0x1 0x1
305 #define MX8MQ_IOMUXC_SAI1_RXD1_CORESIGHT_TRACE1 0x168 0x3D0 0x000 0x4 0x0
306 #define MX8MQ_IOMUXC_SAI1_RXD1_GPIO4_IO3 0x168 0x3D0 0x000 0x5 0x0
307 #define MX8MQ_IOMUXC_SAI1_RXD1_CCMSRCGPCMIX_BOOT_CFG1 0x168 0x3D0 0x000 0x6 0x0
308 #define MX8MQ_IOMUXC_SAI1_RXD1_SIM_M_HADDR18 0x168 0x3D0 0x000 0x7 0x0
  /src/sys/arch/arm/xilinx/
zynq7000_clkc.c 65 #define PCAP_CLK_CTRL 0x168
  /src/sys/dev/marvell/
ehci_mv.c 93 #define MARVELL_USB_TXTTFILLTUNING 0x168

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