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  /src/sys/dev/isa/
isareg.h 67 #define IO_PMP2 0x178 /* 82347 Power Management Peripheral */
  /src/sys/external/gpl2/dts/dist/include/dt-bindings/clock/
dm816.h 26 #define DM816_TIMER3_CLKCTRL DM816_CLKCTRL_INDEX(0x178)
omap5.h 92 #define OMAP5_UART6_CLKCTRL OMAP5_CLKCTRL_INDEX(0x178)
dra7.h 187 #define DRA7_L4PER2_MCASP5_CLKCTRL DRA7_L4PER2_CLKCTRL_INDEX(0x178)
  /src/sys/arch/hp300/dev/
mtreg.h 35 #define MT7978ID 0x178
  /src/sys/dev/gpib/
mtreg.h 36 #define MT7978ID 0x178
  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_doorbell.h 137 AMDGPU_VEGA20_DOORBELL_IH = 0x178,
191 AMDGPU_NAVI10_DOORBELL_IH = 0x178,
  /src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/arm/
arm-realview-pba8.dts 29 arm,hbi = <0x178>;
  /src/tests/lib/libcurses/tests/
std_defines 103 assign KEY_RESUME 0x178
  /src/sys/arch/amiga/amiga/
cc_registers.h 214 #define R_SPR7_POS 0x178
  /src/sys/arch/arm/footbridge/
dc21285reg.h 289 #define UART_FLAGS 0x178
  /src/sys/dev/ic/
igsfbreg.h 365 #define IGS_COP_DST_START_REG 0x178
  /src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/nxp/vf/
vf610-pinfunc.h 598 #define VF610_PAD_PTB24__GPIO_94 0x178 0x000 ALT0 0x0
599 #define VF610_PAD_PTB24__SAI0_RX_BCLK 0x178 0x000 ALT1 0x0
600 #define VF610_PAD_PTB24__UART1_RX 0x178 0x37C ALT2 0x2
601 #define VF610_PAD_PTB24__SRC_RCON19 0x178 0x39C ALT3 0x1
602 #define VF610_PAD_PTB24__FB_MUXED_TSIZ0 0x178 0x000 ALT4 0x0
603 #define VF610_PAD_PTB24__NF_WE_B 0x178 0x000 ALT5 0x0
604 #define VF610_PAD_PTB24__UART3_CTS 0x178 0x000 ALT6 0x0
605 #define VF610_PAD_PTB24__DCU1_G4 0x178 0x000 ALT7 0x0
  /src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/broadcom/stingray/
stingray-pinctrl.dtsi 242 0x178 MODE_NITRO /* i2c1_scl */
  /src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/freescale/
imx8mm-pinfunc.h 343 #define MX8MM_IOMUXC_SAI1_RXD5_SAI1_RX_DATA5 0x178 0x3E0 0x000 0x0 0x0
344 #define MX8MM_IOMUXC_SAI1_RXD5_SAI6_TX_DATA0 0x178 0x3E0 0x000 0x1 0x0
345 #define MX8MM_IOMUXC_SAI1_RXD5_SAI6_RX_DATA0 0x178 0x3E0 0x514 0x2 0x0
346 #define MX8MM_IOMUXC_SAI1_RXD5_SAI1_RX_SYNC 0x178 0x3E0 0x4C4 0x3 0x1
347 #define MX8MM_IOMUXC_SAI1_RXD5_CORESIGHT_TRACE5 0x178 0x3E0 0x000 0x4 0x0
348 #define MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x178 0x3E0 0x000 0x5 0x0
349 #define MX8MM_IOMUXC_SAI1_RXD5_CCMSRCGPCMIX_BOOT_CFG5 0x178 0x3E0 0x000 0x6 0x0
350 #define MX8MM_IOMUXC_SAI1_RXD5_SIM_M_HADDR22 0x178 0x3E0 0x000 0x7 0x0
imx8mq-pinfunc.h 328 #define MX8MQ_IOMUXC_SAI1_RXD5_SAI1_RX_DATA5 0x178 0x3E0 0x000 0x0 0x0
329 #define MX8MQ_IOMUXC_SAI1_RXD5_SAI6_TX_DATA0 0x178 0x3E0 0x000 0x1 0x0
330 #define MX8MQ_IOMUXC_SAI1_RXD5_SAI6_RX_DATA0 0x178 0x3E0 0x514 0x2 0x0
331 #define MX8MQ_IOMUXC_SAI1_RXD5_SAI1_RX_SYNC 0x178 0x3E0 0x4C4 0x3 0x1
332 #define MX8MQ_IOMUXC_SAI1_RXD5_CORESIGHT_TRACE5 0x178 0x3E0 0x000 0x4 0x0
333 #define MX8MQ_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x178 0x3E0 0x000 0x5 0x0
334 #define MX8MQ_IOMUXC_SAI1_RXD5_CCMSRCGPCMIX_BOOT_CFG5 0x178 0x3E0 0x000 0x6 0x0
335 #define MX8MQ_IOMUXC_SAI1_RXD5_SIM_M_HADDR22 0x178 0x3E0 0x000 0x7 0x0
  /src/lib/libcurses/
keyname.c 343 if (key == 0x178) {
  /src/sys/arch/arm/imx/
imx23_digctlreg.h 295 #define HW_DIGCTL_OCRAM_STATUS6_CLR 0x178
  /src/sys/arch/arm/nvidia/
tegra210_pinmux.c 155 TEGRA_PIN("shutdown", 0x178, NULL, NULL, NULL, NULL),
tegra_hdmireg.h 243 #define HDMI_NV_PDISP_SOR_BLANK_REG 0x178
  /src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/nxp/imx/
imx25-pinfunc.h 407 #define MX25_PAD_UART1_RTS__UART1_RTS 0x178 0x370 0x000 0x00 0x000
408 #define MX25_PAD_UART1_RTS__CSI_D0 0x178 0x370 0x488 0x01 0x001
409 #define MX25_PAD_UART1_RTS__GPT3_CAPIN1 0x178 0x370 0x000 0x02 0x000
410 #define MX25_PAD_UART1_RTS__UART2_DCD 0x178 0x370 0x000 0x03 0x000
411 #define MX25_PAD_UART1_RTS__GPIO_4_24 0x178 0x370 0x000 0x05 0x000
imx6dl-pinfunc.h 468 #define MX6QDL_PAD_EIM_D29__EIM_DATA29 0x178 0x548 0x000 0x0 0x0
469 #define MX6QDL_PAD_EIM_D29__IPU1_DI1_PIN15 0x178 0x548 0x000 0x1 0x0
470 #define MX6QDL_PAD_EIM_D29__ECSPI4_SS0 0x178 0x548 0x808 0x2 0x1
471 #define MX6QDL_PAD_EIM_D29__UART2_RTS_B 0x178 0x548 0x900 0x4 0x1
472 #define MX6QDL_PAD_EIM_D29__UART2_CTS_B 0x178 0x548 0x000 0x4 0x0
473 #define MX6QDL_PAD_EIM_D29__UART2_DTE_RTS_B 0x178 0x548 0x000 0x4 0x0
474 #define MX6QDL_PAD_EIM_D29__UART2_DTE_CTS_B 0x178 0x548 0x900 0x4 0x1
475 #define MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x178 0x548 0x000 0x5 0x0
476 #define MX6QDL_PAD_EIM_D29__IPU1_CSI1_VSYNC 0x178 0x548 0x8bc 0x6 0x0
477 #define MX6QDL_PAD_EIM_D29__IPU1_DI0_PIN14 0x178 0x548 0x000 0x7 0x
    [all...]
imxrt1050-pinfunc.h 729 #define MXRT1050_IOMUXC_GPIO_B0_15_LCD_DATA11 0x178 0x368 0x000 0x0 0x0
730 #define MXRT1050_IOMUXC_GPIO_B0_15_XBAR_INOUT13 0x178 0x368 0x000 0x1 0x0
731 #define MXRT1050_IOMUXC_GPIO_B0_15_ARM_CM7_RXEV 0x178 0x368 0x000 0x2 0x0
732 #define MXRT1050_IOMUXC_GPIO_B0_15_SAI1_RX_BCLK 0x178 0x368 0x590 0x3 0x2
733 #define MXRT1050_IOMUXC_GPIO_B0_15_FLEXIO2_D15 0x178 0x368 0x000 0x4 0x0
734 #define MXRT1050_IOMUXC_GPIO_B0_15_GPIO2_IO15 0x178 0x368 0x000 0x5 0x0
735 #define MXRT1050_IOMUXC_GPIO_B0_15_SRC_BT_CFG11 0x178 0x368 0x000 0x6 0x0
imxrt1170-pinfunc.h 1017 #define IOMUXC_GPIO_AD_27_LPUART1_RTS_B 0x178 0x3BC 0x0 0x0 0x0
1018 #define IOMUXC_GPIO_AD_27_LPSPI2_SIN 0x178 0x3BC 0x5E8 0x1 0x0
1019 #define IOMUXC_GPIO_AD_27_SEMC_CSX02 0x178 0x3BC 0x0 0x2 0x0
1020 #define IOMUXC_GPIO_AD_27_ENET_RX_DATA01 0x178 0x3BC 0x4B4 0x3 0x0
1021 #define IOMUXC_GPIO_AD_27_FLEXPWM2_PWM1_B 0x178 0x3BC 0x528 0x4 0x1
1022 #define IOMUXC_GPIO_AD_27_GPIO_MUX3_IO26 0x178 0x3BC 0x0 0x5 0x0
1023 #define IOMUXC_GPIO_AD_27_KPP_COL04 0x178 0x3BC 0x0 0x6 0x0
1024 #define IOMUXC_GPIO_AD_27_FLEXIO2_D27 0x178 0x3BC 0x0 0x8 0x0
1025 #define IOMUXC_GPIO_AD_27_ENET_QOS_MDIO 0x178 0x3BC 0x4EC 0x9 0x1
1026 #define IOMUXC_GPIO_AD_27_GPIO9_IO26 0x178 0x3BC 0x0 0xA 0x
    [all...]
  /src/sys/arch/m68k/060sp/dist/
fplsp.doc 187 0x178: _060LSP__fremx_

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