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  /src/sys/external/gpl2/dts/dist/include/dt-bindings/clock/
dm816.h 29 #define DM816_TIMER6_CLKCTRL DM816_CLKCTRL_INDEX(0x184)
  /src/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/falcon/
nouveau_nvkm_falcon_v1.c 49 nvkm_falcon_wr32(falcon, 0x184 + (port * 16), ((u32 *)data)[i]);
62 nvkm_falcon_wr32(falcon, 0x184 + (port * 16),
69 nvkm_falcon_wr32(falcon, 0x184 + (port * 16), 0);
  /src/sys/arch/arm/sunxi/
sunxi_can.h 135 #define SUNXI_CAN_RBUF_RBACK1 0x184
  /src/sys/dev/pcmcia/
if_cnwreg.h 99 #define CNW_EREG_STAT_RXERR 0x184
  /src/sys/arch/arm/ti/
omap2_gpmcreg.h 109 #define GPMC_CONFIG2_6 0x184
132 #define GPMC_CONFIG2_6 0x184
  /src/sys/arch/arm/ixp12x0/
ixp12x0_pcireg.h 151 #define IXPPCI_IRQ_RAW_STATUS (IXP12X0_PCI_VBASE + 0x184)
  /src/sys/arch/hpcmips/tx/
tx39ioreg.h 39 #define TX39_IOMFIODATAOUT_REG 0x184
  /src/sys/arch/sh3/include/
pcicreg.h 78 #define SH4_PCIDLA0 (SH4_PCIC+0x184) /* 32bit */
  /src/sys/dev/pci/
if_nfereg.h 71 #define NFE_SETUP_R4 0x184
cs4281reg.h 139 #define CS4281_FCR1 0x184 /* FIFO Control Register 1 */
  /src/sys/arch/arm/marvell/
mvsocreg.h 137 #define MVSOC_MLMB_WINCR(w) (((w) << 3) + 0x184)
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/smu/
smu_8_0_d.h 164 #define mmMP_SMUIF2_MP0PUB_IND_INDEX 0x184
199 #define mmMP0PUB_IND_INDEX_2 0x184
447 #define mmPWRHW2_PWRHW_SMC_IND_INDEX 0x184
  /src/tests/lib/libcurses/tests/
std_defines 115 assign KEY_SEXIT 0x184
  /src/sys/arch/amiga/amiga/
cc_registers.h 220 #define R_COLOR02 0x184
  /src/sys/arch/arm/footbridge/
dc21285reg.h 332 #define IRQ_RAW_STATUS 0x184
  /src/sys/arch/hpcmips/vr/
icureg.h 340 #define VR4102_FIRINT_REG_W 0x184 /* Level2 FIR intr reg */
  /src/sys/dev/sbus/
p9100reg.h 143 #define VID_MEM_CONFIG 0x184 /* memory config */
  /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/inc/
cz_ppsmc.h 151 #define PPSMC_MSG_AllowLowSclkInterrupt ((uint16_t) 0x184)
  /src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/broadcom/stingray/
stingray-pinctrl.dtsi 250 0x184 MODE_NITRO /* sdio0_data0 */
  /src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/
hi3620-hi4511.dts 201 0x184 0x0 /* SPI1_CLK/SPI1_DI (IOMG98) */
208 0x184 0x1 /* GPIO (IOMG98) */
456 0x184 0 /* I2C1_SCL (IOCFG105) */
  /src/lib/libcurses/
keyname.c 391 if (key == 0x184) {
  /src/sys/arch/arm/imx/
imx23_digctlreg.h 304 #define HW_DIGCTL_OCRAM_STATUS7_SET 0x184
  /src/sys/arch/arm/nvidia/
tegra210_pinmux.c 158 TEGRA_PIN("dvfs_pwm_pbb1", 0x184, "rsvd0", "cldvfs", "spi3", "rsvd3"),
tegra_hdmireg.h 258 #define HDMI_NV_PDISP_SOR_SEQ_INST1_REG 0x184
  /src/sys/arch/powerpc/include/ibm4xx/
dcr4xx.h 201 #define DCR_MAL0_TXCASR 0x184 /* Tx Channel Active Register (Set) */

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