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Searched
refs:x194
(Results
1 - 25
of
58
) sorted by relevancy
1
2
3
/src/sys/arch/evbppc/stand/wii/
boot.c
48
#define HW_RESETS (HW_BASE + 0
x194
)
/src/sys/external/gpl2/dts/dist/include/dt-bindings/clock/
dm816.h
33
#define DM816_MAILBOX_CLKCTRL DM816_CLKCTRL_INDEX(0
x194
)
/src/sys/arch/arm/sunxi/
sunxi_can.h
139
#define SUNXI_CAN_RBUF_RBACK5 0
x194
/src/sys/dev/ic/
universereg.h
62
u_int32_t _space7[(0x1a0-0
x194
)/4];
/src/sys/dev/pcmcia/
if_cnwreg.h
105
#define CNW_EREG_STAT_TXABORT 0
x194
/src/sys/arch/arm/ti/
omap2_gpmcreg.h
110
#define GPMC_CONFIG6_6 0
x194
133
#define GPMC_CONFIG6_6 0
x194
/src/sys/arch/arm/broadcom/
bcm2835_cm.h
131
#define CM_PULSEDIV 0
x194
/src/sys/arch/evbppc/include/
wii.h
151
#define HW_RESETS (HOLLYWOOD_PRIV_BASE + 0
x194
)
/src/sys/arch/hpcmips/tx/
tx39ioreg.h
43
#define TX39_IOIOPOWERDWN_REG 0
x194
/src/sys/arch/sh3/include/
pcicreg.h
82
#define SH4_PCIDLA1 (SH4_PCIC+0
x194
) /* 32bit */
/src/sys/dev/pci/
if_nfereg.h
75
#define NFE_PHY_DATA 0
x194
cs4281reg.h
147
#define CS4281_FPDR1 0
x194
/* FIFO Polled Data Register 1 */
/src/tests/lib/libcurses/tests/
std_defines
131
assign KEY_SSAVE 0
x194
/src/sys/arch/amiga/amiga/
cc_registers.h
228
#define R_COLOR0A 0
x194
/src/sys/dev/sbus/
p9100reg.h
147
#define VID_RLCUR 0
x194
/* RAS low current */
/src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/smu/
smu_8_0_d.h
172
#define mmMP_SMUIF10_MP0PUB_IND_INDEX 0
x194
215
#define mmMP0PUB_IND_INDEX_10 0
x194
/src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/nxp/vf/
vf610-pinfunc.h
647
#define VF610_PAD_PTC28__GPIO_101 0
x194
0x000 ALT0 0x0
648
#define VF610_PAD_PTC28__SAI1_RX_DATA 0
x194
0x000 ALT1 0x0
649
#define VF610_PAD_PTC28__DSPI0_CS3 0
x194
0x000 ALT2 0x0
650
#define VF610_PAD_PTC28__SRC_RCON26 0
x194
0x000 ALT3 0x0
651
#define VF610_PAD_PTC28__FB_BE2_B 0
x194
0x000 ALT4 0x0
652
#define VF610_PAD_PTC28__FB_CS2_B 0
x194
0x000 ALT5 0x0
653
#define VF610_PAD_PTC28__NF_CLE 0
x194
0x000 ALT6 0x0
654
#define VF610_PAD_PTC28__DCU1_B3 0
x194
0x000 ALT7 0x0
/src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/broadcom/stingray/
stingray-pinctrl.dtsi
254
0
x194
MODE_NITRO /* sdio0_data4 */
/src/lib/libcurses/
keyname.c
455
if (key == 0
x194
) {
/src/sys/arch/arm/imx/
imx23_digctlreg.h
314
#define HW_DIGCTL_OCRAM_STATUS8_SET 0
x194
/src/sys/arch/arm/nvidia/
tegra210_pinmux.c
162
TEGRA_PIN("pcc7", 0
x194
, "rsvd0", "rsvd1", "rsvd2", "rsvd3"),
tegra_hdmireg.h
262
#define HDMI_NV_PDISP_SOR_SEQ_INST5_REG 0
x194
/src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/nxp/imx/
imxrt1050-pinfunc.h
783
#define MXRT1050_IOMUXC_GPIO_B1_06_LCD_DATA18 0
x194
0x384 0x000 0x0 0x0
784
#define MXRT1050_IOMUXC_GPIO_B1_06_LPSPI4_SDO 0
x194
0x384 0x528 0x1 0x1
785
#define MXRT1050_IOMUXC_GPIO_B1_06_CSI_DATA13 0
x194
0x384 0x000 0x2 0x0
786
#define MXRT1050_IOMUXC_GPIO_B1_06_ENET_RX_EN 0
x194
0x384 0x43C 0x3 0x1
787
#define MXRT1050_IOMUXC_GPIO_B1_06_FLEXIO2_D22 0
x194
0x384 0x000 0x4 0x0
788
#define MXRT1050_IOMUXC_GPIO_B1_06_GPIO2_IO22 0
x194
0x384 0x000 0x5 0x0
/src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/freescale/
imx8mm-pinfunc.h
388
#define MX8MM_IOMUXC_SAI1_TXD2_SAI1_TX_DATA2 0
x194
0x3FC 0x000 0x0 0x0
389
#define MX8MM_IOMUXC_SAI1_TXD2_SAI5_TX_DATA2 0
x194
0x3FC 0x000 0x1 0x0
390
#define MX8MM_IOMUXC_SAI1_TXD2_CORESIGHT_TRACE10 0
x194
0x3FC 0x000 0x4 0x0
391
#define MX8MM_IOMUXC_SAI1_TXD2_GPIO4_IO14 0
x194
0x3FC 0x000 0x5 0x0
392
#define MX8MM_IOMUXC_SAI1_TXD2_CCMSRCGPCMIX_BOOT_CFG10 0
x194
0x3FC 0x000 0x6 0x0
393
#define MX8MM_IOMUXC_SAI1_TXD2_SIM_M_HADDR29 0
x194
0x3FC 0x000 0x7 0x0
imx8mq-pinfunc.h
373
#define MX8MQ_IOMUXC_SAI1_TXD2_SAI1_TX_DATA2 0
x194
0x3FC 0x000 0x0 0x0
374
#define MX8MQ_IOMUXC_SAI1_TXD2_SAI5_TX_DATA2 0
x194
0x3FC 0x000 0x1 0x0
375
#define MX8MQ_IOMUXC_SAI1_TXD2_CORESIGHT_TRACE10 0
x194
0x3FC 0x000 0x4 0x0
376
#define MX8MQ_IOMUXC_SAI1_TXD2_GPIO4_IO14 0
x194
0x3FC 0x000 0x5 0x0
377
#define MX8MQ_IOMUXC_SAI1_TXD2_CCMSRCGPCMIX_BOOT_CFG10 0
x194
0x3FC 0x000 0x6 0x0
378
#define MX8MQ_IOMUXC_SAI1_TXD2_SIM_M_HADDR29 0
x194
0x3FC 0x000 0x7 0x0
Completed in 68 milliseconds
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Indexes created Tue Feb 24 01:34:59 UTC 2026