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  /src/sys/arch/x86/pci/
lpssreg.h 51 #define LPSS_TXACK 0x218
  /src/sys/external/gpl2/dts/dist/include/dt-bindings/clock/
lpc18xx-ccu.h 24 #define CLK_APB1_I2S 0x218
  /src/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/engine/gr/
nouveau_nvkm_engine_gr_ctxgf104.c 104 .attrib_nr = 0x218,
nouveau_nvkm_engine_gr_ctxgk110b.c 97 .attrib_nr = 0x218,
nouveau_nvkm_engine_gr_ctxgf119.c 520 .attrib_nr = 0x218,
522 .alpha_nr = 0x218,
nouveau_nvkm_engine_gr_ctxgf117.c 304 .attrib_nr = 0x218,
nouveau_nvkm_engine_gr_ctxgf110.c 352 .attrib_nr = 0x218,
nouveau_nvkm_engine_gr_ctxgf108.c 805 .attrib_nr = 0x218,
807 .alpha_nr = 0x218,
  /src/sys/arch/arm/cortex/
pl310_reg.h 100 #define L2C_INT_MASK_STS 0x218
  /src/sys/arch/arm/marvell/
kirkwoodreg.h 175 #define KIRKWOOD_MLMB_MFIQIMHR 0x218 /*Main FIQ Interrupt High Mask*/
mv78xx0reg.h 174 #define MV78XX0_ICI_IRQSCR 0x218 /* IRQ Select Cause */
dovereg.h 152 #define DOVE_DB_SMFIQIMR 0x218 /* Second Main FIQ intr Mask */
  /src/sys/arch/mips/adm5120/include/
adm5120reg.h 309 #define ADM5120_MPMC_SWT(__i) (0x218 + 0x020 * (__i))
  /src/sys/arch/arm/ti/
omap2_gpmcreg.h 161 #define GPMC_ECC7_RESULT 0x218
  /src/sys/arch/sparc64/dev/
ffbreg.h 157 #define FFB_FBC_XCLIP 0x218
  /src/sys/dev/ic/
igsfbreg.h 301 #define IGS_COP_DST_MAP_WIDTH_REG 0x218
  /src/sys/dev/pci/
cs4281reg.h 153 #define CS4281_FSIC2 0x218 /* FIFO Status and Interrupt Control Register 2 */
  /src/external/lgpl3/gmp/dist/mpn/cray/ieee/
invert_limb.c 72 0x219, 0x218, 0x216, 0x215, 0x214, 0x213, 0x212, 0x211,
  /src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/broadcom/stingray/
stingray-pinctrl.dtsi 314 0x218 MODE_NAND /* uart0_cts */
  /src/sys/arch/arm/nvidia/
tegra210_pinmux.c 195 TEGRA_PIN("touch_clk_pv7", 0x218, "touch", "rsvd1", "rsvd2", "rsvd3"),
  /src/sys/arch/powerpc/include/oea/
spr.h 112 #define SPR_DBAT0U 0x218 /* ..6. Data BAT Reg 0 Upper */
  /src/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/engine/fifo/
nouveau_nvkm_engine_fifo_gpfifogv100.c 221 nvkm_mo32(chan->base.inst, 0x218, 0x00000000, 0x00000000);
  /src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/nxp/imx/
imxrt1050-pinfunc.h 54 #define MXRT1050_IOMUXC_GPIO_EMC_05_SEMC_DA05 0x028 0x218 0x000 0x0 0x0
55 #define MXRT1050_IOMUXC_GPIO_EMC_05_FLEXPWM4_PWM2_B 0x028 0x218 0x000 0x1 0x0
56 #define MXRT1050_IOMUXC_GPIO_EMC_05_SAI2_TX_SYNC 0x028 0x218 0x5C4 0x2 0x0
57 #define MXRT1050_IOMUXC_GPIO_EMC_05_XBAR_INOUT7 0x028 0x218 0x620 0x3 0x0
58 #define MXRT1050_IOMUXC_GPIO_EMC_05_FLEXIO1_D05 0x028 0x218 0x000 0x4 0x0
59 #define MXRT1050_IOMUXC_GPIO_EMC_05_GPIO4_IO05 0x028 0x218 0x000 0x5 0x0
imx6sl-pinfunc.h 842 #define MX6SL_PAD_LCD_RESET__LCD_RESET 0x218 0x520 0x000 0x0 0x0
843 #define MX6SL_PAD_LCD_RESET__EIM_DTACK_B 0x218 0x520 0x880 0x1 0x1
844 #define MX6SL_PAD_LCD_RESET__LCD_BUSY 0x218 0x520 0x774 0x2 0x1
845 #define MX6SL_PAD_LCD_RESET__EIM_WAIT_B 0x218 0x520 0x884 0x3 0x1
846 #define MX6SL_PAD_LCD_RESET__UART2_CTS_B 0x218 0x520 0x000 0x4 0x0
847 #define MX6SL_PAD_LCD_RESET__UART2_RTS_B 0x218 0x520 0x800 0x4 0x2
848 #define MX6SL_PAD_LCD_RESET__GPIO2_IO19 0x218 0x520 0x000 0x5 0x0
849 #define MX6SL_PAD_LCD_RESET__CCM_PMIC_READY 0x218 0x520 0x62c 0x6 0x1
  /src/sys/arch/m68k/060sp/dist/
fplsp.doc 207 0x218: _060LSP__ftentoxd_

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