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  /src/sys/dev/usb/
if_urtwnreg.h 48 #define R92E_AUTO_LLT 0x224
  /src/sys/arch/x86/pci/
lpssreg.h 63 #define LPSS_TX_IRQ_CLR 0x224
  /src/sys/external/gpl2/dts/dist/include/dt-bindings/clock/
dm814.h 37 #define DM814_MMC3_CLKCTRL DM814_CLKCTRL_INDEX(0x224)
  /src/sys/arch/arm/sunxi/
sunxi_tconreg.h 73 #define SUNXI_TCON_LVDS_ANA1 0x224
  /src/sys/dev/pci/
pciide_sis_reg.h 111 {0x9f4, 0x64a, 0x474, 0x254, 0x234, 0x224, 0x214};
  /src/sys/arch/arm/marvell/
mv78xx0reg.h 177 #define MV78XX0_ICI_FIQIMHR 0x224 /* FIQ Interrupt Mask High */
  /src/sys/arch/sparc64/dev/
ffbreg.h 160 #define FFB_FBC_VCLIPMAX 0x224
  /src/sys/dev/ic/
mvsatareg.h 164 #define DMA_C 0x224 /* Basic DMA Command */
  /src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/broadcom/stingray/
stingray-pinctrl.dtsi 317 0x224 MODE_NAND /* uart0_dsr */
  /src/sys/arch/arm/nvidia/
tegra210_pinmux.c 198 TEGRA_PIN("motion_int_px2", 0x224, "rsvd0", "rsvd1", "rsvd2", "rsvd3"),
  /src/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/engine/fifo/
nouveau_nvkm_engine_fifo_gpfifogv100.c 223 nvkm_wo32(chan->base.inst, 0x224, upper_32_bits(mthd));
  /src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/
hi3620-hi4511.dts 398 0x224 0 /* UART2_RTS (IOCFG145) */
408 0x224 0 /* GPIO (IOCFG145) */
imx50-pinfunc.h 740 #define MX50_PAD_EPDC_PWRCTRL0__EPCD_PWRCTRL0 0x224 0x5c0 0x000 0x0 0x0
741 #define MX50_PAD_EPDC_PWRCTRL0__GPIO3_29 0x224 0x5c0 0x000 0x1 0x0
742 #define MX50_PAD_EPDC_PWRCTRL0__EIM_WEIM_D_29 0x224 0x5c0 0x000 0x2 0x0
743 #define MX50_PAD_EPDC_PWRCTRL0__ELCDIF_DAT_13 0x224 0x5c0 0x730 0x3 0x1
744 #define MX50_PAD_EPDC_PWRCTRL0__AUDMUX_AUD4_RXD 0x224 0x5c0 0x6c4 0x4 0x1
745 #define MX50_PAD_EPDC_PWRCTRL0__SDMA_DEBUG_RTBUFFER_WRITE 0x224 0x5c0 0x000 0x6 0x0
746 #define MX50_PAD_EPDC_PWRCTRL0__USBPHY2_AVALID 0x224 0x5c0 0x000 0x7 0x0
imx6q-pinfunc.h 653 #define MX6QDL_PAD_GPIO_1__ESAI_RX_CLK 0x224 0x5f4 0x86c 0x0 0x1
654 #define MX6QDL_PAD_GPIO_1__WDOG2_B 0x224 0x5f4 0x000 0x1 0x0
655 #define MX6QDL_PAD_GPIO_1__KEY_ROW5 0x224 0x5f4 0x8f4 0x2 0x0
656 #define MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x224 0x5f4 0x004 0x3 0xff0d0101
657 #define MX6QDL_PAD_GPIO_1__PWM2_OUT 0x224 0x5f4 0x000 0x4 0x0
658 #define MX6QDL_PAD_GPIO_1__GPIO1_IO01 0x224 0x5f4 0x000 0x5 0x0
659 #define MX6QDL_PAD_GPIO_1__SD1_CD_B 0x224 0x5f4 0x000 0x6 0x0
imx6sl-pinfunc.h 865 #define MX6SL_PAD_REF_CLK_24M__XTALOSC_REF_CLK_24M 0x224 0x52c 0x000 0x0 0x0
866 #define MX6SL_PAD_REF_CLK_24M__I2C3_SCL 0x224 0x52c 0x72c 0x1 0x2
867 #define MX6SL_PAD_REF_CLK_24M__PWM3_OUT 0x224 0x52c 0x000 0x2 0x0
868 #define MX6SL_PAD_REF_CLK_24M__USB_OTG2_ID 0x224 0x52c 0x5e0 0x3 0x2
869 #define MX6SL_PAD_REF_CLK_24M__CCM_PMIC_READY 0x224 0x52c 0x62c 0x4 0x2
870 #define MX6SL_PAD_REF_CLK_24M__GPIO3_IO21 0x224 0x52c 0x000 0x5 0x0
871 #define MX6SL_PAD_REF_CLK_24M__SD3_WP 0x224 0x52c 0x84c 0x6 0x3
imx35-pinfunc.h 568 #define MX35_PAD_D3_REV__IPU_DISPB_D3_REV 0x224 0x688 0x000 0x0 0x0
569 #define MX35_PAD_D3_REV__IPU_DISPB_SER_RS 0x224 0x688 0x000 0x2 0x0
570 #define MX35_PAD_D3_REV__GPIO1_3 0x224 0x688 0x84c 0x5 0x1
571 #define MX35_PAD_D3_REV__SDMA_DEBUG_BUS_RWB 0x224 0x688 0x000 0x6 0x0
572 #define MX35_PAD_D3_REV__ARM11P_TOP_TRACE_20 0x224 0x688 0x000 0x7 0x0
imx6dl-pinfunc.h 734 #define MX6QDL_PAD_GPIO_2__ESAI_TX_FS 0x224 0x5f4 0x830 0x0 0x1
735 #define MX6QDL_PAD_GPIO_2__KEY_ROW6 0x224 0x5f4 0x8d0 0x2 0x1
736 #define MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x224 0x5f4 0x000 0x5 0x0
737 #define MX6QDL_PAD_GPIO_2__SD2_WP 0x224 0x5f4 0x000 0x6 0x0
738 #define MX6QDL_PAD_GPIO_2__MLB_DATA 0x224 0x5f4 0x8e0 0x7 0x1
imx51-pinfunc.h 424 #define MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK 0x224 0x614 0x000 0x0 0x0
425 #define MX51_PAD_CSPI1_SCLK__GPIO4_27 0x224 0x614 0x000 0x3 0x0
426 #define MX51_PAD_CSPI1_SCLK__I2C1_SCL 0x224 0x614 0x9b0 0x1 0x1
  /src/sys/arch/arm/broadcom/
bcm53xx_reg.h 480 #define PCIE_MSI_CTRL_5 0x224
867 #define GMAC_RCVPTR 0x224
  /src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/freescale/
imx8mm-pinfunc.h 580 #define MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x224 0x48C 0x000 0x0 0x0
581 #define MX8MM_IOMUXC_I2C3_SCL_PWM4_OUT 0x224 0x48C 0x000 0x1 0x0
582 #define MX8MM_IOMUXC_I2C3_SCL_GPT2_CLK 0x224 0x48C 0x000 0x2 0x0
583 #define MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18 0x224 0x48C 0x000 0x5 0x0
584 #define MX8MM_IOMUXC_I2C3_SCL_TPSMP_HDATA20 0x224 0x48C 0x000 0x7 0x0
imx8mn-pinfunc.h 585 #define MX8MN_IOMUXC_I2C3_SCL_I2C3_SCL 0x224 0x48C 0x588 0x0 0x0
586 #define MX8MN_IOMUXC_I2C3_SCL_PWM4_OUT 0x224 0x48C 0x000 0x1 0x0
587 #define MX8MN_IOMUXC_I2C3_SCL_GPT2_CLK 0x224 0x48C 0x000 0x2 0x0
588 #define MX8MN_IOMUXC_I2C3_SCL_ECSPI2_SCLK 0x224 0x48C 0x580 0x3 0x2
589 #define MX8MN_IOMUXC_I2C3_SCL_GPIO5_IO18 0x224 0x48C 0x000 0x5 0x0
imx8mq-pinfunc.h 548 #define MX8MQ_IOMUXC_I2C3_SCL_I2C3_SCL 0x224 0x48C 0x000 0x0 0x0
549 #define MX8MQ_IOMUXC_I2C3_SCL_PWM4_OUT 0x224 0x48C 0x000 0x1 0x0
550 #define MX8MQ_IOMUXC_I2C3_SCL_GPT2_CLK 0x224 0x48C 0x000 0x2 0x0
551 #define MX8MQ_IOMUXC_I2C3_SCL_GPIO5_IO18 0x224 0x48C 0x000 0x5 0x0
552 #define MX8MQ_IOMUXC_I2C3_SCL_TPSMP_HDATA20 0x224 0x48C 0x000 0x7 0x0
imx8mp-pinfunc.h 738 #define MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x224 0x484 0x000 0x0 0x0
739 #define MX8MP_IOMUXC_UART1_TXD__UART1_DTE_RX 0x224 0x484 0x5E8 0x0 0x5
740 #define MX8MP_IOMUXC_UART1_TXD__ECSPI3_MOSI 0x224 0x484 0x000 0x1 0x0
741 #define MX8MP_IOMUXC_UART1_TXD__GPIO5_IO23 0x224 0x484 0x000 0x5 0x0
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/oss/
oss_2_0_d.h 160 #define ixCLIENT0_OFFSET 0x224
  /src/sys/arch/powerpc/include/booke/
etsecreg.h 257 #define TBASE4 0x224 /* TxBD base address of ring 4 [TSEC3] */

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